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-- Company:
-- Engineer:
--
-- Create Date:    11:38:35 11/15/2018
-- Design Name:
-- Module Name:    domaci2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity domaci2 is
    Port ( iSW : in  STD_LOGIC_VECTOR (7 downto 0);
           iSEL : in  STD_LOGIC;
           oLED : out  STD_LOGIC_VECTOR (7 downto 0));
end domaci2;

architecture Behavioral of domaci2 is
signal sInv : STD_LOGIC_VECTOR (7 downto 0);
	signal sSub : STD_LOGIC_VECTOR (3 downto 0);
	signal sComp : STD_LOGIC;
	signal sCoder : STD_LOGIC_VECTOR (2 downto 0);
	signal sFinal : STD_LOGIC_VECTOR (7 downto 0);
begin
	sSub(3 downto 0) <= std_logic_vector(unsigned(iSW(7 downto 4)) - unsigned(iSW(3 downto 0)));

	sComp <= '0' when iSW(7 downto 4) > iSW(3 downto 0) else
				'1';
	sCoder <= "000" when iSW(0) = '1' else
				 "001" when iSW(1) = '1' else
				 "010" when iSW(2) = '1' else
				 "011" when iSW(3) = '1' else
				 "100" when iSW(4) = '1' else
				 "101" when iSW(5) = '1' else
				 "110" when iSW(6) = '1' else
				 "111";
	sFinal <= sCoder & sComp & sSub when iSEL = '1' else
				 not(iSW(7 downto 0));
		oLED(7) <= sFinal(7);
		oLED(6) <= sFinal(6);
		oLED(5) <= sFinal(5);
		oLED(4) <= sFinal(4);
		oLED(3) <= sFinal(3);
		oLED(2) <= sFinal(2);
		oLED(1) <= sFinal(1);
		oLED(0) <= sFinal(0);

end Behavioral;