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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = < 0x01 >;
  5. #size-cells = < 0x01 >;
  6. compatible = "rockchip,rk3229";
  7. interrupt-parent = < 0x01 >;
  8.  
  9. chosen {
  10. bootargs = "vmalloc=496M psci=enable rockchip_jtag";
  11. };
  12.  
  13. aliases {
  14. serial0 = "/serial@11010000";
  15. serial1 = "/serial@11020000";
  16. serial2 = "/serial@11030000";
  17. i2c0 = "/i2c@11050000";
  18. i2c1 = "/i2c@11060000";
  19. i2c2 = "/i2c@11070000";
  20. i2c3 = "/i2c@11080000";
  21. lcdc0 = "/vop@20050000";
  22. spi0 = "/spi@11090000";
  23. };
  24.  
  25. memory {
  26. device_type = "memory";
  27. reg = < 0x00 0x00 >;
  28. };
  29.  
  30. clocks {
  31. compatible = "rockchip,rk-clocks";
  32. #address-cells = < 0x01 >;
  33. #size-cells = < 0x01 >;
  34. ranges = < 0x00 0x110e0000 0x1000 >;
  35.  
  36. fixed_rate_cons {
  37. compatible = "rockchip,rk-fixed-rate-cons";
  38.  
  39. xin24m {
  40. compatible = "rockchip,rk-fixed-clock";
  41. clock-output-names = "xin24m";
  42. clock-frequency = < 0x16e3600 >;
  43. #clock-cells = < 0x00 >;
  44. linux,phandle = < 0x02 >;
  45. phandle = < 0x02 >;
  46. };
  47.  
  48. xin12m {
  49. compatible = "rockchip,rk-fixed-clock";
  50. clocks = < 0x02 >;
  51. clock-output-names = "xin12m";
  52. clock-frequency = < 0xb71b00 >;
  53. #clock-cells = < 0x00 >;
  54. linux,phandle = < 0x14 >;
  55. phandle = < 0x14 >;
  56. };
  57.  
  58. hdmiphy_out {
  59. compatible = "rockchip,rk-fixed-clock";
  60. clock-output-names = "hdmiphy_out";
  61. clock-frequency = < 0x2367b880 >;
  62. #clock-cells = < 0x00 >;
  63. linux,phandle = < 0x45 >;
  64. phandle = < 0x45 >;
  65. };
  66.  
  67. usbphy0_480m {
  68. compatible = "rockchip,rk-fixed-clock";
  69. clock-output-names = "usbphy0_480m";
  70. clock-frequency = < 0x1c9c3800 >;
  71. #clock-cells = < 0x00 >;
  72. linux,phandle = < 0x46 >;
  73. phandle = < 0x46 >;
  74. };
  75.  
  76. usbphy1_480m {
  77. compatible = "rockchip,rk-fixed-clock";
  78. clock-output-names = "usbphy1_480m";
  79. clock-frequency = < 0x1c9c3800 >;
  80. #clock-cells = < 0x00 >;
  81. linux,phandle = < 0x47 >;
  82. phandle = < 0x47 >;
  83. };
  84.  
  85. jtag_clkin {
  86. compatible = "rockchip,rk-fixed-clock";
  87. clock-output-names = "jtag_clkin";
  88. clock-frequency = < 0x00 >;
  89. #clock-cells = < 0x00 >;
  90. linux,phandle = < 0x4c >;
  91. phandle = < 0x4c >;
  92. };
  93.  
  94. dummy {
  95. compatible = "rockchip,rk-fixed-clock";
  96. clock-output-names = "dummy";
  97. clock-frequency = < 0x00 >;
  98. #clock-cells = < 0x00 >;
  99. linux,phandle = < 0x38 >;
  100. phandle = < 0x38 >;
  101. };
  102.  
  103. gmac_clkin {
  104. compatible = "rockchip,rk-fixed-clock";
  105. clock-output-names = "gmac_clkin";
  106. clock-frequency = < 0x7735940 >;
  107. #clock-cells = < 0x00 >;
  108. linux,phandle = < 0x3c >;
  109. phandle = < 0x3c >;
  110. };
  111.  
  112. phy_50m_out {
  113. compatible = "rockchip,rk-fixed-clock";
  114. clock-output-names = "phy_50m_out";
  115. clock-frequency = < 0x00 >;
  116. #clock-cells = < 0x00 >;
  117. linux,phandle = < 0x3d >;
  118. phandle = < 0x3d >;
  119. };
  120.  
  121. phy_rx_out {
  122. compatible = "rockchip,rk-fixed-clock";
  123. clock-output-names = "phy_rx_out";
  124. clock-frequency = < 0x00 >;
  125. #clock-cells = < 0x00 >;
  126. };
  127.  
  128. phy_tx_out {
  129. compatible = "rockchip,rk-fixed-clock";
  130. clock-output-names = "phy_tx_out";
  131. clock-frequency = < 0x00 >;
  132. #clock-cells = < 0x00 >;
  133. };
  134.  
  135. clkin_hsadc_tsp {
  136. compatible = "rockchip,rk-fixed-clock";
  137. clock-output-names = "clkin_hsadc_tsp";
  138. clock-frequency = < 0x00 >;
  139. #clock-cells = < 0x00 >;
  140. linux,phandle = < 0x53 >;
  141. phandle = < 0x53 >;
  142. };
  143.  
  144. i2s_clkin {
  145. compatible = "rockchip,rk-fixed-clock";
  146. clock-output-names = "i2s_clkin";
  147. clock-frequency = < 0x00 >;
  148. #clock-cells = < 0x00 >;
  149. linux,phandle = < 0x13 >;
  150. phandle = < 0x13 >;
  151. };
  152. };
  153.  
  154. fixed_factor_cons {
  155. compatible = "rockchip,rk-fixed-factor-cons";
  156.  
  157. hclk_rkvdec {
  158. compatible = "rockchip,rk-fixed-factor-clock";
  159. clocks = < 0x03 >;
  160. clock-output-names = "hclk_rkvdec";
  161. clock-div = < 0x04 >;
  162. clock-mult = < 0x01 >;
  163. #clock-cells = < 0x00 >;
  164. linux,phandle = < 0x58 >;
  165. phandle = < 0x58 >;
  166. };
  167.  
  168. hclk_vpu {
  169. compatible = "rockchip,rk-fixed-factor-clock";
  170. clocks = < 0x04 >;
  171. clock-output-names = "hclk_vpu";
  172. clock-div = < 0x04 >;
  173. clock-mult = < 0x01 >;
  174. #clock-cells = < 0x00 >;
  175. linux,phandle = < 0x94 >;
  176. phandle = < 0x94 >;
  177. };
  178.  
  179. xin32k_out {
  180. compatible = "rockchip,rk-fixed-clock";
  181. clocks = < 0x05 >;
  182. clock-output-names = "xin32k_out";
  183. clock-div = < 0x01 >;
  184. clock-mult = < 0x01 >;
  185. #clock-cells = < 0x00 >;
  186. };
  187. };
  188.  
  189. clock_regs {
  190. compatible = "rockchip,rk-clock-regs";
  191. #address-cells = < 0x01 >;
  192. #size-cells = < 0x01 >;
  193. reg = < 0x00 0x1000 >;
  194. ranges;
  195.  
  196. pll_cons {
  197. compatible = "rockchip,rk-pll-cons";
  198. #address-cells = < 0x01 >;
  199. #size-cells = < 0x01 >;
  200. ranges;
  201.  
  202. pll-clk@0000 {
  203. compatible = "rockchip,rk3188-pll-clk";
  204. reg = < 0x00 0x10 >;
  205. mode-reg = < 0x40 0x00 >;
  206. status-reg = < 0x04 0x0a >;
  207. clocks = < 0x02 >;
  208. clock-output-names = "clk_apll";
  209. rockchip,pll-type = < 0x40 >;
  210. #clock-cells = < 0x00 >;
  211. linux,phandle = < 0x07 >;
  212. phandle = < 0x07 >;
  213. };
  214.  
  215. pll-clk@000c {
  216. compatible = "rockchip,rk3188-pll-clk";
  217. reg = < 0x0c 0x10 >;
  218. mode-reg = < 0x40 0x04 >;
  219. status-reg = < 0x10 0x0a >;
  220. clocks = < 0x02 >;
  221. clock-output-names = "clk_dpll";
  222. rockchip,pll-type = < 0x80 >;
  223. #clock-cells = < 0x00 >;
  224. linux,phandle = < 0x09 >;
  225. phandle = < 0x09 >;
  226. };
  227.  
  228. pll-clk@0018 {
  229. compatible = "rockchip,rk3188-pll-clk";
  230. reg = < 0x18 0x10 >;
  231. mode-reg = < 0x40 0x08 >;
  232. status-reg = < 0x1c 0x0a >;
  233. clocks = < 0x02 >;
  234. clock-output-names = "clk_cpll";
  235. rockchip,pll-type = < 0x100 >;
  236. #clock-cells = < 0x00 >;
  237. #clock-init-cells = < 0x01 >;
  238. linux,phandle = < 0x0b >;
  239. phandle = < 0x0b >;
  240. };
  241.  
  242. pll-clk@0024 {
  243. compatible = "rockchip,rk3188-pll-clk";
  244. reg = < 0x24 0x10 >;
  245. mode-reg = < 0x40 0x0c >;
  246. status-reg = < 0x28 0x0a >;
  247. clocks = < 0x02 >;
  248. clock-output-names = "clk_gpll";
  249. rockchip,pll-type = < 0x100 >;
  250. #clock-cells = < 0x00 >;
  251. #clock-init-cells = < 0x01 >;
  252. linux,phandle = < 0x08 >;
  253. phandle = < 0x08 >;
  254. };
  255. };
  256.  
  257. clk_sel_cons {
  258. compatible = "rockchip,rk-sel-cons";
  259. #address-cells = < 0x01 >;
  260. #size-cells = < 0x01 >;
  261. ranges;
  262.  
  263. sel-con@0044 {
  264. compatible = "rockchip,rk3188-selcon";
  265. reg = < 0x44 0x04 >;
  266. #address-cells = < 0x01 >;
  267. #size-cells = < 0x01 >;
  268.  
  269. clk_core_div {
  270. compatible = "rockchip,rk3188-div-con";
  271. rockchip,bits = < 0x00 0x05 >;
  272. clocks = < 0x06 >;
  273. clock-output-names = "clk_core";
  274. rockchip,div-type = < 0x00 >;
  275. #clock-cells = < 0x00 >;
  276. rockchip,clkops-idx = < 0x0b >;
  277. rockchip,flags = < 0xc0 >;
  278. };
  279.  
  280. clk_core_mux {
  281. compatible = "rockchip,rk3188-mux-con";
  282. rockchip,bits = < 0x06 0x02 >;
  283. clocks = < 0x07 0x08 0x09 >;
  284. clock-output-names = "clk_core";
  285. #clock-cells = < 0x00 >;
  286. #clock-init-cells = < 0x01 >;
  287. linux,phandle = < 0x06 >;
  288. phandle = < 0x06 >;
  289. };
  290.  
  291. aclk_bus_div {
  292. compatible = "rockchip,rk3188-div-con";
  293. rockchip,bits = < 0x08 0x05 >;
  294. clocks = < 0x0a >;
  295. clock-output-names = "aclk_bus";
  296. rockchip,div-type = < 0x00 >;
  297. #clock-cells = < 0x00 >;
  298. #clock-init-cells = < 0x01 >;
  299. rockchip,clkops-idx = < 0x01 >;
  300. rockchip,flags = < 0x100 >;
  301. linux,phandle = < 0x0d >;
  302. phandle = < 0x0d >;
  303. };
  304.  
  305. aclk_bus_mux {
  306. compatible = "rockchip,rk3188-mux-con";
  307. rockchip,bits = < 0x0d 0x02 >;
  308. clocks = < 0x0b 0x08 0x0c >;
  309. clock-output-names = "aclk_bus";
  310. #clock-cells = < 0x00 >;
  311. #clock-init-cells = < 0x01 >;
  312. linux,phandle = < 0x0a >;
  313. phandle = < 0x0a >;
  314. };
  315. };
  316.  
  317. sel-con@0048 {
  318. compatible = "rockchip,rk3188-selcon";
  319. reg = < 0x48 0x04 >;
  320. #address-cells = < 0x01 >;
  321. #size-cells = < 0x01 >;
  322.  
  323. pclk_dbg_div {
  324. compatible = "rockchip,rk3188-div-con";
  325. rockchip,bits = < 0x00 0x04 >;
  326. clocks = < 0x06 >;
  327. clock-output-names = "pclk_dbg";
  328. rockchip,div-type = < 0x00 >;
  329. #clock-cells = < 0x00 >;
  330. rockchip,clkops-idx = < 0x0c >;
  331. linux,phandle = < 0x60 >;
  332. phandle = < 0x60 >;
  333. };
  334.  
  335. aclk_core_div {
  336. compatible = "rockchip,rk3188-div-con";
  337. rockchip,bits = < 0x04 0x03 >;
  338. clocks = < 0x06 >;
  339. clock-output-names = "aclk_core";
  340. rockchip,div-type = < 0x00 >;
  341. #clock-cells = < 0x00 >;
  342. rockchip,clkops-idx = < 0x0c >;
  343. linux,phandle = < 0x44 >;
  344. phandle = < 0x44 >;
  345. };
  346.  
  347. hclk_bus_div {
  348. compatible = "rockchip,rk3188-div-con";
  349. rockchip,bits = < 0x08 0x02 >;
  350. clocks = < 0x0d >;
  351. clock-output-names = "hclk_bus";
  352. rockchip,div-type = < 0x00 >;
  353. #clock-cells = < 0x00 >;
  354. #clock-init-cells = < 0x01 >;
  355. linux,phandle = < 0x51 >;
  356. phandle = < 0x51 >;
  357. };
  358.  
  359. pclk_bus_div {
  360. compatible = "rockchip,rk3188-div-con";
  361. rockchip,bits = < 0x0c 0x03 >;
  362. clocks = < 0x0d >;
  363. clock-output-names = "pclk_bus";
  364. rockchip,div-type = < 0x00 >;
  365. #clock-cells = < 0x00 >;
  366. #clock-init-cells = < 0x01 >;
  367. linux,phandle = < 0x4f >;
  368. phandle = < 0x4f >;
  369. };
  370. };
  371.  
  372. sel-con@004c {
  373. compatible = "rockchip,rk3188-selcon";
  374. reg = < 0x4c 0x04 >;
  375. #address-cells = < 0x01 >;
  376. #size-cells = < 0x01 >;
  377.  
  378. hclk_vio_div {
  379. compatible = "rockchip,rk3188-div-con";
  380. rockchip,bits = < 0x00 0x05 >;
  381. clocks = < 0x0e >;
  382. clock-output-names = "hclk_vio";
  383. rockchip,div-type = < 0x00 >;
  384. #clock-cells = < 0x00 >;
  385. #clock-init-cells = < 0x01 >;
  386. linux,phandle = < 0x57 >;
  387. phandle = < 0x57 >;
  388. };
  389.  
  390. clk_nandc_div {
  391. compatible = "rockchip,rk3188-div-con";
  392. rockchip,bits = < 0x08 0x05 >;
  393. clocks = < 0x0f >;
  394. clock-output-names = "clk_nandc";
  395. rockchip,div-type = < 0x00 >;
  396. #clock-cells = < 0x00 >;
  397. rockchip,clkops-idx = < 0x01 >;
  398. rockchip,flags = < 0x100 >;
  399. };
  400.  
  401. clk_nandc_mux {
  402. compatible = "rockchip,rk3188-mux-con";
  403. rockchip,bits = < 0x0e 0x01 >;
  404. clocks = < 0x0b 0x08 >;
  405. clock-output-names = "clk_nandc";
  406. #clock-cells = < 0x00 >;
  407. #clock-init-cells = < 0x01 >;
  408. linux,phandle = < 0x0f >;
  409. phandle = < 0x0f >;
  410. };
  411. };
  412.  
  413. sel-con@0050 {
  414. compatible = "rockchip,rk3188-selcon";
  415. reg = < 0x50 0x04 >;
  416. #address-cells = < 0x01 >;
  417. #size-cells = < 0x01 >;
  418.  
  419. clk_i2s1_pll_div {
  420. compatible = "rockchip,rk3188-div-con";
  421. rockchip,bits = < 0x00 0x07 >;
  422. clocks = < 0x10 >;
  423. clock-output-names = "clk_i2s1_pll";
  424. rockchip,div-type = < 0x00 >;
  425. #clock-cells = < 0x00 >;
  426. rockchip,clkops-idx = < 0x01 >;
  427. rockchip,flags = < 0x180 >;
  428. linux,phandle = < 0x11 >;
  429. phandle = < 0x11 >;
  430. };
  431.  
  432. clk_i2s1_mux {
  433. compatible = "rockchip,rk3188-mux-con";
  434. rockchip,bits = < 0x08 0x02 >;
  435. clocks = < 0x11 0x12 0x13 0x14 >;
  436. clock-output-names = "clk_i2s1";
  437. #clock-cells = < 0x00 >;
  438. rockchip,clkops-idx = < 0x0e >;
  439. rockchip,flags = < 0x04 >;
  440. linux,phandle = < 0x15 >;
  441. phandle = < 0x15 >;
  442. };
  443.  
  444. clk_i2s1_out_mux {
  445. compatible = "rockchip,rk3188-mux-con";
  446. rockchip,bits = < 0x0c 0x01 >;
  447. clocks = < 0x15 0x14 >;
  448. clock-output-names = "clk_i2s1_out";
  449. #clock-cells = < 0x00 >;
  450. linux,phandle = < 0x4b >;
  451. phandle = < 0x4b >;
  452. };
  453.  
  454. i2s1_pll_mux {
  455. compatible = "rockchip,rk3188-mux-con";
  456. rockchip,bits = < 0x0f 0x01 >;
  457. clocks = < 0x0b 0x08 >;
  458. clock-output-names = "clk_i2s1_pll";
  459. #clock-cells = < 0x00 >;
  460. #clock-init-cells = < 0x01 >;
  461. linux,phandle = < 0x10 >;
  462. phandle = < 0x10 >;
  463. };
  464. };
  465.  
  466. sel-con@0054 {
  467. compatible = "rockchip,rk3188-selcon";
  468. reg = < 0x54 0x04 >;
  469. #address-cells = < 0x01 >;
  470. #size-cells = < 0x01 >;
  471.  
  472. testclk_div {
  473. compatible = "rockchip,rk3188-div-con";
  474. rockchip,bits = < 0x00 0x05 >;
  475. clocks = < 0x16 >;
  476. clock-output-names = "testclk";
  477. rockchip,div-type = < 0x00 >;
  478. #clock-cells = < 0x00 >;
  479. rockchip,clkops-idx = < 0x01 >;
  480. };
  481.  
  482. clk_24m_div {
  483. compatible = "rockchip,rk3188-div-con";
  484. rockchip,bits = < 0x08 0x05 >;
  485. clocks = < 0x02 >;
  486. clock-output-names = "clk_24m";
  487. rockchip,div-type = < 0x00 >;
  488. #clock-cells = < 0x00 >;
  489. rockchip,clkops-idx = < 0x01 >;
  490. };
  491. };
  492.  
  493. sel-con@0058 {
  494. compatible = "rockchip,rk3188-selcon";
  495. reg = < 0x58 0x04 >;
  496. #address-cells = < 0x01 >;
  497. #size-cells = < 0x01 >;
  498.  
  499. clk_mac_pll_div {
  500. compatible = "rockchip,rk3188-div-con";
  501. rockchip,bits = < 0x00 0x05 >;
  502. clocks = < 0x17 >;
  503. clock-output-names = "clk_mac_pll";
  504. rockchip,div-type = < 0x00 >;
  505. #clock-cells = < 0x00 >;
  506. rockchip,clkops-idx = < 0x01 >;
  507. rockchip,flags = < 0x100 >;
  508. linux,phandle = < 0x3e >;
  509. phandle = < 0x3e >;
  510. };
  511.  
  512. clk_mac_mux {
  513. compatible = "rockchip,rk3188-mux-con";
  514. rockchip,bits = < 0x05 0x01 >;
  515. clocks = < 0x17 0x18 >;
  516. clock-output-names = "clk_mac";
  517. #clock-cells = < 0x00 >;
  518. rockchip,flags = < 0x04 >;
  519. #clock-init-cells = < 0x01 >;
  520. linux,phandle = < 0x4e >;
  521. phandle = < 0x4e >;
  522. };
  523.  
  524. clk_mac_pll_mux {
  525. compatible = "rockchip,rk3188-mux-con";
  526. rockchip,bits = < 0x07 0x01 >;
  527. clocks = < 0x0b 0x08 >;
  528. clock-output-names = "clk_mac_pll";
  529. #clock-cells = < 0x00 >;
  530. linux,phandle = < 0x17 >;
  531. phandle = < 0x17 >;
  532. };
  533.  
  534. clk_gmac_div {
  535. compatible = "rockchip,rk3188-div-con";
  536. rockchip,bits = < 0x08 0x05 >;
  537. clocks = < 0x19 >;
  538. clock-output-names = "clk_gmac";
  539. rockchip,div-type = < 0x00 >;
  540. #clock-cells = < 0x00 >;
  541. rockchip,clkops-idx = < 0x01 >;
  542. rockchip,flags = < 0x100 >;
  543. };
  544.  
  545. clk_gmac_mux {
  546. compatible = "rockchip,rk3188-mux-con";
  547. rockchip,bits = < 0x0f 0x01 >;
  548. clocks = < 0x0b 0x08 >;
  549. clock-output-names = "clk_gmac";
  550. #clock-cells = < 0x00 >;
  551. #clock-init-cells = < 0x01 >;
  552. linux,phandle = < 0x19 >;
  553. phandle = < 0x19 >;
  554. };
  555. };
  556.  
  557. sel-con@005c {
  558. compatible = "rockchip,rk3188-selcon";
  559. reg = < 0x5c 0x04 >;
  560. #address-cells = < 0x01 >;
  561. #size-cells = < 0x01 >;
  562.  
  563. spdif_div {
  564. compatible = "rockchip,rk3188-div-con";
  565. rockchip,bits = < 0x00 0x07 >;
  566. clocks = < 0x1a >;
  567. clock-output-names = "clk_spdif_pll";
  568. rockchip,div-type = < 0x00 >;
  569. #clock-cells = < 0x00 >;
  570. rockchip,clkops-idx = < 0x01 >;
  571. rockchip,flags = < 0x180 >;
  572. linux,phandle = < 0x1b >;
  573. phandle = < 0x1b >;
  574. };
  575.  
  576. spdif_mux {
  577. compatible = "rockchip,rk3188-mux-con";
  578. rockchip,bits = < 0x08 0x02 >;
  579. clocks = < 0x1b 0x1c 0x14 >;
  580. clock-output-names = "clk_spdif";
  581. #clock-cells = < 0x00 >;
  582. rockchip,clkops-idx = < 0x0e >;
  583. rockchip,flags = < 0x04 >;
  584. linux,phandle = < 0x8a >;
  585. phandle = < 0x8a >;
  586. };
  587.  
  588. spdif_pll_mux {
  589. compatible = "rockchip,rk3188-mux-con";
  590. rockchip,bits = < 0x0f 0x01 >;
  591. clocks = < 0x0b 0x08 >;
  592. clock-output-names = "clk_spdif_pll";
  593. #clock-cells = < 0x00 >;
  594. #clock-init-cells = < 0x01 >;
  595. linux,phandle = < 0x1a >;
  596. phandle = < 0x1a >;
  597. };
  598. };
  599.  
  600. sel-con@0060 {
  601. compatible = "rockchip,rk3188-selcon";
  602. reg = < 0x60 0x04 >;
  603. #address-cells = < 0x01 >;
  604. #size-cells = < 0x01 >;
  605.  
  606. i2s1_frac {
  607. compatible = "rockchip,rk3188-frac-con";
  608. clocks = < 0x11 >;
  609. clock-output-names = "i2s1_frac";
  610. rockchip,bits = < 0x00 0x20 >;
  611. rockchip,clkops-idx = < 0x05 >;
  612. #clock-cells = < 0x00 >;
  613. linux,phandle = < 0x12 >;
  614. phandle = < 0x12 >;
  615. };
  616. };
  617.  
  618. sel-con@0064 {
  619. compatible = "rockchip,rk3188-selcon";
  620. reg = < 0x64 0x04 >;
  621. #address-cells = < 0x01 >;
  622. #size-cells = < 0x01 >;
  623.  
  624. i2s0_frac {
  625. compatible = "rockchip,rk3188-frac-con";
  626. clocks = < 0x1d >;
  627. clock-output-names = "i2s0_frac";
  628. rockchip,bits = < 0x00 0x20 >;
  629. rockchip,clkops-idx = < 0x05 >;
  630. #clock-cells = < 0x00 >;
  631. linux,phandle = < 0x1f >;
  632. phandle = < 0x1f >;
  633. };
  634. };
  635.  
  636. sel-con@0068 {
  637. compatible = "rockchip,rk3188-selcon";
  638. reg = < 0x68 0x04 >;
  639. #address-cells = < 0x01 >;
  640. #size-cells = < 0x01 >;
  641.  
  642. clk_i2s0_pll_div {
  643. compatible = "rockchip,rk3188-div-con";
  644. rockchip,bits = < 0x00 0x07 >;
  645. clocks = < 0x1e >;
  646. clock-output-names = "clk_i2s0_pll";
  647. rockchip,div-type = < 0x00 >;
  648. #clock-cells = < 0x00 >;
  649. rockchip,clkops-idx = < 0x01 >;
  650. rockchip,flags = < 0x180 >;
  651. linux,phandle = < 0x1d >;
  652. phandle = < 0x1d >;
  653. };
  654.  
  655. clk_i2s0_mux {
  656. compatible = "rockchip,rk3188-mux-con";
  657. rockchip,bits = < 0x08 0x02 >;
  658. clocks = < 0x1d 0x1f 0x13 0x14 >;
  659. clock-output-names = "clk_i2s0";
  660. #clock-cells = < 0x00 >;
  661. rockchip,clkops-idx = < 0x0e >;
  662. rockchip,flags = < 0x04 >;
  663. linux,phandle = < 0x49 >;
  664. phandle = < 0x49 >;
  665. };
  666.  
  667. i2s0_pll_mux {
  668. compatible = "rockchip,rk3188-mux-con";
  669. rockchip,bits = < 0x0f 0x01 >;
  670. clocks = < 0x0b 0x08 >;
  671. clock-output-names = "clk_i2s0_pll";
  672. #clock-cells = < 0x00 >;
  673. #clock-init-cells = < 0x01 >;
  674. linux,phandle = < 0x1e >;
  675. phandle = < 0x1e >;
  676. };
  677. };
  678.  
  679. sel-con@006c {
  680. compatible = "rockchip,rk3188-selcon";
  681. reg = < 0x6c 0x04 >;
  682. #address-cells = < 0x01 >;
  683. #size-cells = < 0x01 >;
  684.  
  685. aclk_peri_div {
  686. compatible = "rockchip,rk3188-div-con";
  687. rockchip,bits = < 0x00 0x05 >;
  688. clocks = < 0x20 >;
  689. clock-output-names = "aclk_peri";
  690. rockchip,div-type = < 0x00 >;
  691. #clock-cells = < 0x00 >;
  692. rockchip,clkops-idx = < 0x01 >;
  693. rockchip,flags = < 0x100 >;
  694. };
  695.  
  696. hclk_peri_div {
  697. compatible = "rockchip,rk3188-div-con";
  698. rockchip,bits = < 0x08 0x02 >;
  699. clocks = < 0x20 >;
  700. clock-output-names = "hclk_peri";
  701. rockchip,div-type = < 0x80 >;
  702. rockchip,div-relations = < 0x00 0x01 0x01 0x02 0x02 0x04 >;
  703. #clock-cells = < 0x00 >;
  704. #clock-init-cells = < 0x01 >;
  705. linux,phandle = < 0x54 >;
  706. phandle = < 0x54 >;
  707. };
  708.  
  709. aclk_peri_mux {
  710. compatible = "rockchip,rk3188-mux-con";
  711. rockchip,bits = < 0x0a 0x02 >;
  712. clocks = < 0x0b 0x08 0x0c >;
  713. clock-output-names = "aclk_peri";
  714. #clock-cells = < 0x00 >;
  715. #clock-init-cells = < 0x01 >;
  716. linux,phandle = < 0x20 >;
  717. phandle = < 0x20 >;
  718. };
  719.  
  720. pclk_peri_div {
  721. compatible = "rockchip,rk3188-div-con";
  722. rockchip,bits = < 0x0c 0x02 >;
  723. clocks = < 0x20 >;
  724. clock-output-names = "pclk_peri";
  725. rockchip,div-type = < 0x80 >;
  726. rockchip,div-relations = < 0x00 0x01 0x01 0x02 0x02 0x04 0x03 0x08 >;
  727. #clock-cells = < 0x00 >;
  728. #clock-init-cells = < 0x01 >;
  729. linux,phandle = < 0x55 >;
  730. phandle = < 0x55 >;
  731. };
  732. };
  733.  
  734. sel-con@0070 {
  735. compatible = "rockchip,rk3188-selcon";
  736. reg = < 0x70 0x04 >;
  737. #address-cells = < 0x01 >;
  738. #size-cells = < 0x01 >;
  739.  
  740. clk_sdmmc0_div {
  741. compatible = "rockchip,rk3188-div-con";
  742. rockchip,bits = < 0x00 0x08 >;
  743. clocks = < 0x21 >;
  744. clock-output-names = "clk_sdmmc0";
  745. rockchip,div-type = < 0x00 >;
  746. #clock-cells = < 0x00 >;
  747. rockchip,clkops-idx = < 0x03 >;
  748. rockchip,flags = < 0x100 >;
  749. };
  750.  
  751. clk_sdmmc0_mux {
  752. compatible = "rockchip,rk3188-mux-con";
  753. rockchip,bits = < 0x08 0x02 >;
  754. clocks = < 0x0b 0x08 0x02 0x22 >;
  755. clock-output-names = "clk_sdmmc0";
  756. #clock-cells = < 0x00 >;
  757. #clock-init-cells = < 0x01 >;
  758. linux,phandle = < 0x21 >;
  759. phandle = < 0x21 >;
  760. };
  761.  
  762. clk_sdio_mux {
  763. compatible = "rockchip,rk3188-mux-con";
  764. rockchip,bits = < 0x0a 0x02 >;
  765. clocks = < 0x0b 0x08 0x02 0x22 >;
  766. clock-output-names = "clk_sdio";
  767. #clock-cells = < 0x00 >;
  768. #clock-init-cells = < 0x01 >;
  769. linux,phandle = < 0x23 >;
  770. phandle = < 0x23 >;
  771. };
  772.  
  773. clk_emmc_mux {
  774. compatible = "rockchip,rk3188-mux-con";
  775. rockchip,bits = < 0x0c 0x02 >;
  776. clocks = < 0x0b 0x08 0x02 0x22 >;
  777. clock-output-names = "clk_emmc";
  778. #clock-cells = < 0x00 >;
  779. #clock-init-cells = < 0x01 >;
  780. linux,phandle = < 0x24 >;
  781. phandle = < 0x24 >;
  782. };
  783. };
  784.  
  785. sel-con@0074 {
  786. compatible = "rockchip,rk3188-selcon";
  787. reg = < 0x74 0x04 >;
  788. #address-cells = < 0x01 >;
  789. #size-cells = < 0x01 >;
  790.  
  791. clk_sdio_div {
  792. compatible = "rockchip,rk3188-div-con";
  793. rockchip,bits = < 0x00 0x08 >;
  794. clocks = < 0x23 >;
  795. clock-output-names = "clk_sdio";
  796. rockchip,div-type = < 0x00 >;
  797. #clock-cells = < 0x00 >;
  798. rockchip,clkops-idx = < 0x03 >;
  799. rockchip,flags = < 0x100 >;
  800. };
  801.  
  802. clk_emmc_div {
  803. compatible = "rockchip,rk3188-div-con";
  804. rockchip,bits = < 0x08 0x08 >;
  805. clocks = < 0x24 >;
  806. clock-output-names = "clk_emmc";
  807. rockchip,div-type = < 0x00 >;
  808. #clock-cells = < 0x00 >;
  809. rockchip,clkops-idx = < 0x03 >;
  810. rockchip,flags = < 0x100 >;
  811. };
  812. };
  813.  
  814. sel-con@0078 {
  815. compatible = "rockchip,rk3188-selcon";
  816. reg = < 0x78 0x04 >;
  817. #address-cells = < 0x01 >;
  818. #size-cells = < 0x01 >;
  819.  
  820. clk_uart0_pll_div {
  821. compatible = "rockchip,rk3188-div-con";
  822. rockchip,bits = < 0x00 0x07 >;
  823. clocks = < 0x25 >;
  824. clock-output-names = "clk_uart0_pll";
  825. rockchip,div-type = < 0x00 >;
  826. #clock-cells = < 0x00 >;
  827. rockchip,flags = < 0x100 >;
  828. linux,phandle = < 0x26 >;
  829. phandle = < 0x26 >;
  830. };
  831.  
  832. clk_uart0_mux {
  833. compatible = "rockchip,rk3188-mux-con";
  834. rockchip,bits = < 0x08 0x02 >;
  835. clocks = < 0x26 0x27 0x02 >;
  836. clock-output-names = "clk_uart0";
  837. #clock-cells = < 0x00 >;
  838. rockchip,clkops-idx = < 0x0e >;
  839. rockchip,flags = < 0x04 >;
  840. linux,phandle = < 0x68 >;
  841. phandle = < 0x68 >;
  842. };
  843.  
  844. clk_uart0_pll_mux {
  845. compatible = "rockchip,rk3188-mux-con";
  846. rockchip,bits = < 0x0c 0x02 >;
  847. clocks = < 0x0b 0x08 0x22 >;
  848. clock-output-names = "clk_uart0_pll";
  849. #clock-cells = < 0x00 >;
  850. #clock-init-cells = < 0x01 >;
  851. linux,phandle = < 0x25 >;
  852. phandle = < 0x25 >;
  853. };
  854. };
  855.  
  856. sel-con@007c {
  857. compatible = "rockchip,rk3188-selcon";
  858. reg = < 0x7c 0x04 >;
  859. #address-cells = < 0x01 >;
  860. #size-cells = < 0x01 >;
  861.  
  862. clk_uart1_pll_div {
  863. compatible = "rockchip,rk3188-div-con";
  864. rockchip,bits = < 0x00 0x07 >;
  865. clocks = < 0x28 >;
  866. clock-output-names = "clk_uart1_pll";
  867. rockchip,div-type = < 0x00 >;
  868. #clock-cells = < 0x00 >;
  869. rockchip,flags = < 0x100 >;
  870. linux,phandle = < 0x29 >;
  871. phandle = < 0x29 >;
  872. };
  873.  
  874. clk_uart1_mux {
  875. compatible = "rockchip,rk3188-mux-con";
  876. rockchip,bits = < 0x08 0x02 >;
  877. clocks = < 0x29 0x2a 0x02 >;
  878. clock-output-names = "clk_uart1";
  879. #clock-cells = < 0x00 >;
  880. rockchip,clkops-idx = < 0x0e >;
  881. rockchip,flags = < 0x04 >;
  882. linux,phandle = < 0x6d >;
  883. phandle = < 0x6d >;
  884. };
  885.  
  886. clk_uart1_pll_mux {
  887. compatible = "rockchip,rk3188-mux-con";
  888. rockchip,bits = < 0x0c 0x02 >;
  889. clocks = < 0x0b 0x08 0x22 >;
  890. clock-output-names = "clk_uart1_pll";
  891. #clock-cells = < 0x00 >;
  892. #clock-init-cells = < 0x01 >;
  893. linux,phandle = < 0x28 >;
  894. phandle = < 0x28 >;
  895. };
  896. };
  897.  
  898. sel-con@0080 {
  899. compatible = "rockchip,rk3188-selcon";
  900. reg = < 0x80 0x04 >;
  901. #address-cells = < 0x01 >;
  902. #size-cells = < 0x01 >;
  903.  
  904. clk_uart2_pll_div {
  905. compatible = "rockchip,rk3188-div-con";
  906. rockchip,bits = < 0x00 0x07 >;
  907. clocks = < 0x2b >;
  908. clock-output-names = "clk_uart2_pll";
  909. rockchip,div-type = < 0x00 >;
  910. #clock-cells = < 0x00 >;
  911. rockchip,flags = < 0x100 >;
  912. linux,phandle = < 0x30 >;
  913. phandle = < 0x30 >;
  914. };
  915.  
  916. clk_uart2_mux {
  917. compatible = "rockchip,rk3188-mux-con";
  918. rockchip,bits = < 0x08 0x02 >;
  919. clocks = < 0x2b 0x2c 0x02 >;
  920. clock-output-names = "clk_uart2";
  921. #clock-cells = < 0x00 >;
  922. rockchip,clkops-idx = < 0x0e >;
  923. rockchip,flags = < 0x04 >;
  924. linux,phandle = < 0x70 >;
  925. phandle = < 0x70 >;
  926. };
  927.  
  928. clk_uart2_pll_mux {
  929. compatible = "rockchip,rk3188-mux-con";
  930. rockchip,bits = < 0x0c 0x02 >;
  931. clocks = < 0x0b 0x08 0x22 >;
  932. clock-output-names = "clk_uart2_pll";
  933. #clock-cells = < 0x00 >;
  934. #clock-init-cells = < 0x01 >;
  935. linux,phandle = < 0x2b >;
  936. phandle = < 0x2b >;
  937. };
  938. };
  939.  
  940. sel-con@0084 {
  941. compatible = "rockchip,rk3188-selcon";
  942. reg = < 0x84 0x04 >;
  943. #address-cells = < 0x01 >;
  944. #size-cells = < 0x01 >;
  945.  
  946. i2s2_pll_div {
  947. compatible = "rockchip,rk3188-div-con";
  948. rockchip,bits = < 0x00 0x07 >;
  949. clocks = < 0x2d >;
  950. clock-output-names = "clk_i2s2_pll";
  951. rockchip,div-type = < 0x00 >;
  952. #clock-cells = < 0x00 >;
  953. rockchip,clkops-idx = < 0x01 >;
  954. rockchip,flags = < 0x180 >;
  955. linux,phandle = < 0x2e >;
  956. phandle = < 0x2e >;
  957. };
  958.  
  959. clk_i2s2_mux {
  960. compatible = "rockchip,rk3188-mux-con";
  961. rockchip,bits = < 0x08 0x02 >;
  962. clocks = < 0x2e 0x2f 0x13 0x14 >;
  963. clock-output-names = "clk_i2s2";
  964. #clock-cells = < 0x00 >;
  965. rockchip,clkops-idx = < 0x0e >;
  966. rockchip,flags = < 0x04 >;
  967. linux,phandle = < 0x4a >;
  968. phandle = < 0x4a >;
  969. };
  970.  
  971. i2s2_pll_mux {
  972. compatible = "rockchip,rk3188-mux-con";
  973. rockchip,bits = < 0x0f 0x01 >;
  974. clocks = < 0x0b 0x08 >;
  975. clock-output-names = "clk_i2s2_pll";
  976. #clock-cells = < 0x00 >;
  977. #clock-init-cells = < 0x01 >;
  978. linux,phandle = < 0x2d >;
  979. phandle = < 0x2d >;
  980. };
  981. };
  982.  
  983. sel-con@0088 {
  984. compatible = "rockchip,rk3188-selcon";
  985. reg = < 0x88 0x04 >;
  986. #address-cells = < 0x01 >;
  987. #size-cells = < 0x01 >;
  988.  
  989. uart0_frac {
  990. compatible = "rockchip,rk3188-frac-con";
  991. clocks = < 0x26 >;
  992. clock-output-names = "uart0_frac";
  993. rockchip,bits = < 0x00 0x20 >;
  994. rockchip,clkops-idx = < 0x05 >;
  995. #clock-cells = < 0x00 >;
  996. linux,phandle = < 0x27 >;
  997. phandle = < 0x27 >;
  998. };
  999. };
  1000.  
  1001. sel-con@008c {
  1002. compatible = "rockchip,rk3188-selcon";
  1003. reg = < 0x8c 0x04 >;
  1004. #address-cells = < 0x01 >;
  1005. #size-cells = < 0x01 >;
  1006.  
  1007. uart1_frac {
  1008. compatible = "rockchip,rk3188-frac-con";
  1009. clocks = < 0x29 >;
  1010. clock-output-names = "uart1_frac";
  1011. rockchip,bits = < 0x00 0x20 >;
  1012. rockchip,clkops-idx = < 0x05 >;
  1013. #clock-cells = < 0x00 >;
  1014. linux,phandle = < 0x2a >;
  1015. phandle = < 0x2a >;
  1016. };
  1017. };
  1018.  
  1019. sel-con@0090 {
  1020. compatible = "rockchip,rk3188-selcon";
  1021. reg = < 0x90 0x04 >;
  1022. #address-cells = < 0x01 >;
  1023. #size-cells = < 0x01 >;
  1024.  
  1025. uart2_frac {
  1026. compatible = "rockchip,rk3188-frac-con";
  1027. clocks = < 0x30 >;
  1028. clock-output-names = "uart2_frac";
  1029. rockchip,bits = < 0x00 0x20 >;
  1030. rockchip,clkops-idx = < 0x05 >;
  1031. #clock-cells = < 0x00 >;
  1032. linux,phandle = < 0x2c >;
  1033. phandle = < 0x2c >;
  1034. };
  1035. };
  1036.  
  1037. sel-con@0094 {
  1038. compatible = "rockchip,rk3188-selcon";
  1039. reg = < 0x94 0x04 >;
  1040. #address-cells = < 0x01 >;
  1041. #size-cells = < 0x01 >;
  1042.  
  1043. spdif_frac {
  1044. compatible = "rockchip,rk3188-frac-con";
  1045. clocks = < 0x1b >;
  1046. clock-output-names = "spdif_frac";
  1047. rockchip,bits = < 0x00 0x20 >;
  1048. rockchip,clkops-idx = < 0x05 >;
  1049. #clock-cells = < 0x00 >;
  1050. linux,phandle = < 0x1c >;
  1051. phandle = < 0x1c >;
  1052. };
  1053. };
  1054.  
  1055. sel-con@0098 {
  1056. compatible = "rockchip,rk3188-selcon";
  1057. reg = < 0x98 0x04 >;
  1058. #address-cells = < 0x01 >;
  1059. #size-cells = < 0x01 >;
  1060.  
  1061. clk_hdmi_cec_div {
  1062. compatible = "rockchip,rk3188-div-con";
  1063. rockchip,bits = < 0x00 0x0e >;
  1064. clocks = < 0x02 >;
  1065. clock-output-names = "clk_hdmi_cec";
  1066. rockchip,div-type = < 0x00 >;
  1067. #clock-cells = < 0x00 >;
  1068. rockchip,clkops-idx = < 0x01 >;
  1069. linux,phandle = < 0x05 >;
  1070. phandle = < 0x05 >;
  1071. };
  1072. };
  1073.  
  1074. sel-con@009c {
  1075. compatible = "rockchip,rk3188-selcon";
  1076. reg = < 0x9c 0x04 >;
  1077. #address-cells = < 0x01 >;
  1078. #size-cells = < 0x01 >;
  1079.  
  1080. clk_rga_div {
  1081. compatible = "rockchip,rk3188-div-con";
  1082. rockchip,bits = < 0x00 0x05 >;
  1083. clocks = < 0x31 >;
  1084. clock-output-names = "clk_rga";
  1085. rockchip,div-type = < 0x00 >;
  1086. #clock-cells = < 0x00 >;
  1087. rockchip,clkops-idx = < 0x01 >;
  1088. rockchip,flags = < 0x100 >;
  1089. };
  1090.  
  1091. clk_tsp_div {
  1092. compatible = "rockchip,rk3188-div-con";
  1093. rockchip,bits = < 0x08 0x05 >;
  1094. clocks = < 0x32 >;
  1095. clock-output-names = "clk_tsp";
  1096. rockchip,div-type = < 0x00 >;
  1097. #clock-cells = < 0x00 >;
  1098. rockchip,clkops-idx = < 0x01 >;
  1099. rockchip,flags = < 0x100 >;
  1100. };
  1101.  
  1102. clk_tsp_mux {
  1103. compatible = "rockchip,rk3188-mux-con";
  1104. rockchip,bits = < 0x0f 0x01 >;
  1105. clocks = < 0x0b 0x08 >;
  1106. clock-output-names = "clk_tsp";
  1107. #clock-cells = < 0x00 >;
  1108. linux,phandle = < 0x32 >;
  1109. phandle = < 0x32 >;
  1110. };
  1111. };
  1112.  
  1113. sel-con@00a0 {
  1114. compatible = "rockchip,rk3188-selcon";
  1115. reg = < 0xa0 0x04 >;
  1116. #address-cells = < 0x01 >;
  1117. #size-cells = < 0x01 >;
  1118.  
  1119. clk_wifi_div {
  1120. compatible = "rockchip,rk3188-div-con";
  1121. rockchip,bits = < 0x00 0x05 >;
  1122. clocks = < 0x33 >;
  1123. clock-output-names = "clk_wifi";
  1124. rockchip,div-type = < 0x00 >;
  1125. #clock-cells = < 0x00 >;
  1126. rockchip,clkops-idx = < 0x01 >;
  1127. rockchip,flags = < 0x100 >;
  1128. };
  1129.  
  1130. clk_wifi_mux {
  1131. compatible = "rockchip,rk3188-mux-con";
  1132. rockchip,bits = < 0x05 0x02 >;
  1133. clocks = < 0x0b 0x08 0x22 >;
  1134. clock-output-names = "clk_wifi";
  1135. #clock-cells = < 0x00 >;
  1136. linux,phandle = < 0x33 >;
  1137. phandle = < 0x33 >;
  1138. };
  1139.  
  1140. clk_hdcp_div {
  1141. compatible = "rockchip,rk3188-div-con";
  1142. rockchip,bits = < 0x08 0x06 >;
  1143. clocks = < 0x34 >;
  1144. clock-output-names = "clk_hdcp";
  1145. rockchip,div-type = < 0x00 >;
  1146. #clock-cells = < 0x00 >;
  1147. rockchip,clkops-idx = < 0x01 >;
  1148. rockchip,flags = < 0x100 >;
  1149. };
  1150.  
  1151. clk_hdcp_mux {
  1152. compatible = "rockchip,rk3188-mux-con";
  1153. rockchip,bits = < 0x0e 0x02 >;
  1154. clocks = < 0x0b 0x08 0x0c >;
  1155. clock-output-names = "clk_hdcp";
  1156. #clock-cells = < 0x00 >;
  1157. linux,phandle = < 0x34 >;
  1158. phandle = < 0x34 >;
  1159. };
  1160. };
  1161.  
  1162. sel-con@00a4 {
  1163. compatible = "rockchip,rk3188-selcon";
  1164. reg = < 0xa4 0x04 >;
  1165. #address-cells = < 0x01 >;
  1166. #size-cells = < 0x01 >;
  1167.  
  1168. clk_crypto_div {
  1169. compatible = "rockchip,rk3188-div-con";
  1170. rockchip,bits = < 0x00 0x05 >;
  1171. clocks = < 0x35 >;
  1172. clock-output-names = "clk_crypto";
  1173. rockchip,div-type = < 0x00 >;
  1174. #clock-cells = < 0x00 >;
  1175. #clock-init-cells = < 0x01 >;
  1176. rockchip,flags = < 0x100 >;
  1177. };
  1178.  
  1179. clk_crypto_mux {
  1180. compatible = "rockchip,rk3188-mux-con";
  1181. rockchip,bits = < 0x05 0x01 >;
  1182. clocks = < 0x0b 0x08 >;
  1183. clock-output-names = "clk_crypto";
  1184. #clock-cells = < 0x00 >;
  1185. linux,phandle = < 0x35 >;
  1186. phandle = < 0x35 >;
  1187. };
  1188.  
  1189. clk_tsadc_div {
  1190. compatible = "rockchip,rk3188-div-con";
  1191. rockchip,bits = < 0x06 0x0a >;
  1192. clocks = < 0x02 >;
  1193. clock-output-names = "clk_tsadc";
  1194. rockchip,div-type = < 0x00 >;
  1195. #clock-cells = < 0x00 >;
  1196. #clock-init-cells = < 0x01 >;
  1197. linux,phandle = < 0x4d >;
  1198. phandle = < 0x4d >;
  1199. };
  1200. };
  1201.  
  1202. sel-con@00a8 {
  1203. compatible = "rockchip,rk3188-selcon";
  1204. reg = < 0xa8 0x04 >;
  1205. #address-cells = < 0x01 >;
  1206. #size-cells = < 0x01 >;
  1207.  
  1208. clk_spi0_div {
  1209. compatible = "rockchip,rk3188-div-con";
  1210. rockchip,bits = < 0x00 0x07 >;
  1211. clocks = < 0x36 >;
  1212. clock-output-names = "clk_spi0";
  1213. rockchip,div-type = < 0x00 >;
  1214. #clock-cells = < 0x00 >;
  1215. rockchip,clkops-idx = < 0x01 >;
  1216. rockchip,flags = < 0x100 >;
  1217. };
  1218.  
  1219. clk_spi0_mux {
  1220. compatible = "rockchip,rk3188-mux-con";
  1221. rockchip,bits = < 0x08 0x01 >;
  1222. clocks = < 0x0b 0x08 >;
  1223. clock-output-names = "clk_spi0";
  1224. #clock-cells = < 0x00 >;
  1225. linux,phandle = < 0x36 >;
  1226. phandle = < 0x36 >;
  1227. };
  1228. };
  1229.  
  1230. sel-con@00ac {
  1231. compatible = "rockchip,rk3188-selcon";
  1232. reg = < 0xac 0x04 >;
  1233. #address-cells = < 0x01 >;
  1234. #size-cells = < 0x01 >;
  1235.  
  1236. clk_ddr_div {
  1237. compatible = "rockchip,rk3188-div-con";
  1238. rockchip,bits = < 0x00 0x02 >;
  1239. clocks = < 0x37 >;
  1240. clock-output-names = "clk_ddr";
  1241. rockchip,div-type = < 0x80 >;
  1242. rockchip,div-relations = < 0x00 0x01 0x01 0x02 0x03 0x04 >;
  1243. #clock-cells = < 0x00 >;
  1244. rockchip,flags = < 0xc0 >;
  1245. rockchip,clkops-idx = < 0x12 >;
  1246. linux,phandle = < 0x50 >;
  1247. phandle = < 0x50 >;
  1248. };
  1249.  
  1250. clk_ddr_pll_mux {
  1251. compatible = "rockchip,rk3188-mux-con";
  1252. rockchip,bits = < 0x08 0x02 >;
  1253. clocks = < 0x09 0x08 0x07 >;
  1254. clock-output-names = "clk_ddr";
  1255. #clock-cells = < 0x00 >;
  1256. linux,phandle = < 0x37 >;
  1257. phandle = < 0x37 >;
  1258. };
  1259. };
  1260.  
  1261. sel-con@00b0 {
  1262. compatible = "rockchip,rk3188-selcon";
  1263. reg = < 0xb0 0x04 >;
  1264. #address-cells = < 0x01 >;
  1265. #size-cells = < 0x01 >;
  1266.  
  1267. dclk_vop0_pll_mux {
  1268. compatible = "rockchip,rk3188-mux-con";
  1269. rockchip,bits = < 0x00 0x01 >;
  1270. clocks = < 0x08 0x0b >;
  1271. clock-output-names = "dclk_vop0_pll";
  1272. #clock-cells = < 0x00 >;
  1273. #clock-init-cells = < 0x01 >;
  1274. linux,phandle = < 0x39 >;
  1275. phandle = < 0x39 >;
  1276. };
  1277.  
  1278. dclk_vop0_mux {
  1279. compatible = "rockchip,rk3188-mux-con";
  1280. rockchip,bits = < 0x01 0x01 >;
  1281. clocks = < 0x0c 0x38 >;
  1282. clock-output-names = "dclk_vop0";
  1283. #clock-cells = < 0x00 >;
  1284. #clock-init-cells = < 0x01 >;
  1285. linux,phandle = < 0x5f >;
  1286. phandle = < 0x5f >;
  1287. };
  1288.  
  1289. dclk_vop0_div {
  1290. compatible = "rockchip,rk3188-div-con";
  1291. rockchip,bits = < 0x08 0x08 >;
  1292. clocks = < 0x39 >;
  1293. clock-output-names = "dclk_vop0";
  1294. rockchip,div-type = < 0x00 >;
  1295. #clock-cells = < 0x00 >;
  1296. rockchip,clkops-idx = < 0x01 >;
  1297. };
  1298. };
  1299.  
  1300. sel-con@00b4 {
  1301. compatible = "rockchip,rk3188-selcon";
  1302. reg = < 0xb4 0x04 >;
  1303. #address-cells = < 0x01 >;
  1304. #size-cells = < 0x01 >;
  1305.  
  1306. aclk_rkvdec_div {
  1307. compatible = "rockchip,rk3188-div-con";
  1308. rockchip,bits = < 0x00 0x05 >;
  1309. clocks = < 0x03 >;
  1310. clock-output-names = "aclk_rkvdec";
  1311. rockchip,div-type = < 0x00 >;
  1312. #clock-cells = < 0x00 >;
  1313. rockchip,clkops-idx = < 0x01 >;
  1314. rockchip,flags = < 0x100 >;
  1315. };
  1316.  
  1317. aclk_rkvdec_mux {
  1318. compatible = "rockchip,rk3188-mux-con";
  1319. rockchip,bits = < 0x06 0x02 >;
  1320. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1321. clock-output-names = "aclk_rkvdec";
  1322. #clock-cells = < 0x00 >;
  1323. #clock-init-cells = < 0x01 >;
  1324. linux,phandle = < 0x03 >;
  1325. phandle = < 0x03 >;
  1326. };
  1327.  
  1328. clk_vdec_cabac_div {
  1329. compatible = "rockchip,rk3188-div-con";
  1330. rockchip,bits = < 0x08 0x05 >;
  1331. clocks = < 0x3a >;
  1332. clock-output-names = "clk_vdec_cabac";
  1333. rockchip,div-type = < 0x00 >;
  1334. #clock-cells = < 0x00 >;
  1335. rockchip,clkops-idx = < 0x01 >;
  1336. rockchip,flags = < 0x100 >;
  1337. };
  1338.  
  1339. clk_vdec_cabac_mux {
  1340. compatible = "rockchip,rk3188-mux-con";
  1341. rockchip,bits = < 0x0e 0x02 >;
  1342. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1343. clock-output-names = "clk_vdec_cabac";
  1344. #clock-cells = < 0x00 >;
  1345. #clock-init-cells = < 0x01 >;
  1346. linux,phandle = < 0x3a >;
  1347. phandle = < 0x3a >;
  1348. };
  1349. };
  1350.  
  1351. sel-con@00b8 {
  1352. compatible = "rockchip,rk3188-selcon";
  1353. reg = < 0xb8 0x04 >;
  1354. #address-cells = < 0x01 >;
  1355. #size-cells = < 0x01 >;
  1356.  
  1357. dclk_hdmiphy_div {
  1358. compatible = "rockchip,rk3188-div-con";
  1359. rockchip,bits = < 0x00 0x03 >;
  1360. clocks = < 0x39 >;
  1361. clock-output-names = "dclk_hdmiphy";
  1362. rockchip,div-type = < 0x00 >;
  1363. #clock-cells = < 0x00 >;
  1364. rockchip,clkops-idx = < 0x01 >;
  1365. };
  1366.  
  1367. clk_macphy_div {
  1368. compatible = "rockchip,rk3188-div-con";
  1369. rockchip,bits = < 0x08 0x03 >;
  1370. clocks = < 0x3b >;
  1371. clock-output-names = "clk_macphy";
  1372. rockchip,div-type = < 0x00 >;
  1373. #clock-cells = < 0x00 >;
  1374. rockchip,clkops-idx = < 0x01 >;
  1375. };
  1376.  
  1377. mac_clkin {
  1378. compatible = "rockchip,rk3188-mux-con";
  1379. rockchip,bits = < 0x0a 0x01 >;
  1380. clocks = < 0x3c 0x3d >;
  1381. clock-output-names = "mac_clkin";
  1382. #clock-cells = < 0x00 >;
  1383. #clock-init-cells = < 0x01 >;
  1384. linux,phandle = < 0x18 >;
  1385. phandle = < 0x18 >;
  1386. };
  1387.  
  1388. clk_macphy_mux {
  1389. compatible = "rockchip,rk3188-mux-con";
  1390. rockchip,bits = < 0x0c 0x01 >;
  1391. clocks = < 0x3e 0x3c >;
  1392. clock-output-names = "clk_macphy";
  1393. #clock-cells = < 0x00 >;
  1394. #clock-init-cells = < 0x01 >;
  1395. linux,phandle = < 0x3b >;
  1396. phandle = < 0x3b >;
  1397. };
  1398. };
  1399.  
  1400. sel-con@00bc {
  1401. compatible = "rockchip,rk3188-selcon";
  1402. reg = < 0xbc 0x04 >;
  1403. #address-cells = < 0x01 >;
  1404. #size-cells = < 0x01 >;
  1405.  
  1406. i2s2_frac {
  1407. compatible = "rockchip,rk3188-frac-con";
  1408. clocks = < 0x2e >;
  1409. clock-output-names = "i2s2_frac";
  1410. rockchip,bits = < 0x00 0x20 >;
  1411. rockchip,clkops-idx = < 0x05 >;
  1412. #clock-cells = < 0x00 >;
  1413. linux,phandle = < 0x2f >;
  1414. phandle = < 0x2f >;
  1415. };
  1416. };
  1417.  
  1418. sel-con@00c0 {
  1419. compatible = "rockchip,rk3188-selcon";
  1420. reg = < 0xc0 0x04 >;
  1421. #address-cells = < 0x01 >;
  1422. #size-cells = < 0x01 >;
  1423.  
  1424. aclk_iep_div {
  1425. compatible = "rockchip,rk3188-div-con";
  1426. rockchip,bits = < 0x00 0x05 >;
  1427. clocks = < 0x0e >;
  1428. clock-output-names = "aclk_iep";
  1429. rockchip,div-type = < 0x00 >;
  1430. #clock-cells = < 0x00 >;
  1431. rockchip,clkops-idx = < 0x01 >;
  1432. rockchip,flags = < 0x100 >;
  1433. };
  1434.  
  1435. aclk_iep_mux {
  1436. compatible = "rockchip,rk3188-mux-con";
  1437. rockchip,bits = < 0x05 0x02 >;
  1438. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1439. clock-output-names = "aclk_iep";
  1440. #clock-cells = < 0x00 >;
  1441. #clock-init-cells = < 0x01 >;
  1442. linux,phandle = < 0x0e >;
  1443. phandle = < 0x0e >;
  1444. };
  1445.  
  1446. aclk_hdcp_div {
  1447. compatible = "rockchip,rk3188-div-con";
  1448. rockchip,bits = < 0x08 0x05 >;
  1449. clocks = < 0x3f >;
  1450. clock-output-names = "aclk_hdcp";
  1451. rockchip,div-type = < 0x00 >;
  1452. #clock-cells = < 0x00 >;
  1453. rockchip,clkops-idx = < 0x01 >;
  1454. rockchip,flags = < 0x100 >;
  1455. };
  1456.  
  1457. aclk_hdcp_mux {
  1458. compatible = "rockchip,rk3188-mux-con";
  1459. rockchip,bits = < 0x0d 0x02 >;
  1460. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1461. clock-output-names = "aclk_hdcp";
  1462. #clock-cells = < 0x00 >;
  1463. linux,phandle = < 0x3f >;
  1464. phandle = < 0x3f >;
  1465. };
  1466. };
  1467.  
  1468. sel-con@00c4 {
  1469. compatible = "rockchip,rk3188-selcon";
  1470. reg = < 0xc4 0x04 >;
  1471. #address-cells = < 0x01 >;
  1472. #size-cells = < 0x01 >;
  1473.  
  1474. aclk_vpu_div {
  1475. compatible = "rockchip,rk3188-div-con";
  1476. rockchip,bits = < 0x00 0x05 >;
  1477. clocks = < 0x04 >;
  1478. clock-output-names = "aclk_vpu";
  1479. rockchip,div-type = < 0x00 >;
  1480. #clock-cells = < 0x00 >;
  1481. rockchip,clkops-idx = < 0x01 >;
  1482. rockchip,flags = < 0x100 >;
  1483. };
  1484.  
  1485. aclk_vpu_mux {
  1486. compatible = "rockchip,rk3188-mux-con";
  1487. rockchip,bits = < 0x05 0x02 >;
  1488. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1489. clock-output-names = "aclk_vpu";
  1490. #clock-cells = < 0x00 >;
  1491. #clock-init-cells = < 0x01 >;
  1492. linux,phandle = < 0x04 >;
  1493. phandle = < 0x04 >;
  1494. };
  1495. };
  1496.  
  1497. sel-con@00c8 {
  1498. compatible = "rockchip,rk3188-selcon";
  1499. reg = < 0xc8 0x04 >;
  1500. #address-cells = < 0x01 >;
  1501. #size-cells = < 0x01 >;
  1502.  
  1503. aclk_vop_div {
  1504. compatible = "rockchip,rk3188-div-con";
  1505. rockchip,bits = < 0x00 0x05 >;
  1506. clocks = < 0x40 >;
  1507. clock-output-names = "aclk_vop";
  1508. rockchip,div-type = < 0x00 >;
  1509. #clock-cells = < 0x00 >;
  1510. rockchip,clkops-idx = < 0x01 >;
  1511. rockchip,flags = < 0x100 >;
  1512. };
  1513.  
  1514. aclk_vop_mux {
  1515. compatible = "rockchip,rk3188-mux-con";
  1516. rockchip,bits = < 0x05 0x02 >;
  1517. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1518. clock-output-names = "aclk_vop";
  1519. #clock-cells = < 0x00 >;
  1520. #clock-init-cells = < 0x01 >;
  1521. linux,phandle = < 0x40 >;
  1522. phandle = < 0x40 >;
  1523. };
  1524.  
  1525. aclk_rga_div {
  1526. compatible = "rockchip,rk3188-div-con";
  1527. rockchip,bits = < 0x08 0x05 >;
  1528. clocks = < 0x31 >;
  1529. clock-output-names = "aclk_rga";
  1530. rockchip,div-type = < 0x00 >;
  1531. #clock-cells = < 0x00 >;
  1532. rockchip,clkops-idx = < 0x01 >;
  1533. rockchip,flags = < 0x100 >;
  1534. };
  1535.  
  1536. aclk_rga_mux {
  1537. compatible = "rockchip,rk3188-mux-con";
  1538. rockchip,bits = < 0x0d 0x02 >;
  1539. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1540. clock-output-names = "aclk_rga";
  1541. #clock-cells = < 0x00 >;
  1542. #clock-init-cells = < 0x01 >;
  1543. linux,phandle = < 0x31 >;
  1544. phandle = < 0x31 >;
  1545. };
  1546. };
  1547.  
  1548. sel-con@00cc {
  1549. compatible = "rockchip,rk3188-selcon";
  1550. reg = < 0xcc 0x04 >;
  1551. #address-cells = < 0x01 >;
  1552. #size-cells = < 0x01 >;
  1553.  
  1554. clk_gpu_div {
  1555. compatible = "rockchip,rk3188-div-con";
  1556. rockchip,bits = < 0x00 0x05 >;
  1557. clocks = < 0x41 >;
  1558. clock-output-names = "clk_gpu";
  1559. rockchip,div-type = < 0x00 >;
  1560. #clock-cells = < 0x00 >;
  1561. rockchip,clkops-idx = < 0x01 >;
  1562. rockchip,flags = < 0x100 >;
  1563. };
  1564.  
  1565. clk_gpu_mux {
  1566. compatible = "rockchip,rk3188-mux-con";
  1567. rockchip,bits = < 0x05 0x02 >;
  1568. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1569. clock-output-names = "clk_gpu";
  1570. #clock-cells = < 0x00 >;
  1571. #clock-init-cells = < 0x01 >;
  1572. linux,phandle = < 0x41 >;
  1573. phandle = < 0x41 >;
  1574. };
  1575.  
  1576. clk_vdec_core_div {
  1577. compatible = "rockchip,rk3188-div-con";
  1578. rockchip,bits = < 0x08 0x05 >;
  1579. clocks = < 0x42 >;
  1580. clock-output-names = "clk_vdec_core";
  1581. rockchip,div-type = < 0x00 >;
  1582. #clock-cells = < 0x00 >;
  1583. rockchip,clkops-idx = < 0x01 >;
  1584. rockchip,flags = < 0x100 >;
  1585. };
  1586.  
  1587. clk_vdec_core_mux {
  1588. compatible = "rockchip,rk3188-mux-con";
  1589. rockchip,bits = < 0x0d 0x02 >;
  1590. clocks = < 0x0b 0x08 0x0c 0x22 >;
  1591. clock-output-names = "clk_vdec_core";
  1592. #clock-cells = < 0x00 >;
  1593. #clock-init-cells = < 0x01 >;
  1594. linux,phandle = < 0x42 >;
  1595. phandle = < 0x42 >;
  1596. };
  1597. };
  1598.  
  1599. sel-con@0134 {
  1600. compatible = "rockchip,rk3188-selcon";
  1601. reg = < 0x134 0x04 >;
  1602. #address-cells = < 0x01 >;
  1603. #size-cells = < 0x01 >;
  1604.  
  1605. testclk_mux {
  1606. compatible = "rockchip,rk3188-mux-con";
  1607. rockchip,bits = < 0x08 0x04 >;
  1608. clocks = < 0x33 0x38 0x06 0x43 0x00 0x0e 0x41 0x20 0x44 >;
  1609. clock-output-names = "testclk";
  1610. #clock-cells = < 0x00 >;
  1611. #clock-init-cells = < 0x01 >;
  1612. linux,phandle = < 0x16 >;
  1613. phandle = < 0x16 >;
  1614. };
  1615.  
  1616. hdmi_phy_clk_mux {
  1617. compatible = "rockchip,rk3188-mux-con";
  1618. rockchip,bits = < 0x0d 0x01 >;
  1619. clocks = < 0x45 0x02 >;
  1620. clock-output-names = "hdmi_phy_clk";
  1621. #clock-cells = < 0x00 >;
  1622. #clock-init-cells = < 0x01 >;
  1623. linux,phandle = < 0x0c >;
  1624. phandle = < 0x0c >;
  1625. };
  1626.  
  1627. usb480m_phy_mux {
  1628. compatible = "rockchip,rk3188-mux-con";
  1629. rockchip,bits = < 0x0e 0x01 >;
  1630. clocks = < 0x46 0x47 >;
  1631. clock-output-names = "usb480m_phy";
  1632. #clock-cells = < 0x00 >;
  1633. #clock-init-cells = < 0x01 >;
  1634. linux,phandle = < 0x48 >;
  1635. phandle = < 0x48 >;
  1636. };
  1637.  
  1638. usb480m_mux {
  1639. compatible = "rockchip,rk3188-mux-con";
  1640. rockchip,bits = < 0x0f 0x01 >;
  1641. clocks = < 0x48 0x02 >;
  1642. clock-output-names = "usb480m";
  1643. #clock-cells = < 0x00 >;
  1644. rockchip,clkops-idx = < 0x0f >;
  1645. #clock-init-cells = < 0x01 >;
  1646. linux,phandle = < 0x22 >;
  1647. phandle = < 0x22 >;
  1648. };
  1649. };
  1650. };
  1651.  
  1652. clk_gate_cons {
  1653. compatible = "rockchip,rk-gate-cons";
  1654. #address-cells = < 0x01 >;
  1655. #size-cells = < 0x01 >;
  1656. ranges;
  1657.  
  1658. gate-clk@00d0 {
  1659. compatible = "rockchip,rk3188-gate-clk";
  1660. reg = < 0xd0 0x04 >;
  1661. clocks = < 0x38 0x38 0x38 0x1e 0x1f 0x49 0x38 0x2d 0x2f 0x4a 0x10 0x12 0x38 0x4b 0x15 0x16 >;
  1662. clock-output-names = "reserved\0reserved\0reserved\0clk_i2s0_pll\0i2s0_frac\0clk_i2s0\0reserved\0clk_i2s2_pll\0i2s2_frac\0clk_i2s2\0clk_i2s1_pll\0i2s1_frac\0reserved\0clk_i2s1_out\0clk_i2s1\0testclk";
  1663. #clock-cells = < 0x01 >;
  1664. };
  1665.  
  1666. gate-clk@00d4 {
  1667. compatible = "rockchip,rk3188-gate-clk";
  1668. reg = < 0xd4 0x04 >;
  1669. clocks = < 0x0f 0x40 0x31 0x4c 0x3f 0x02 0x02 0x17 0x25 0x27 0x28 0x2a 0x2b 0x2c 0x38 0x38 >;
  1670. clock-output-names = "clk_nandc\0aclk_vop\0aclk_rga\0clk_jtag\0aclk_hdcp\0clk_otgphy0\0clk_otgphy1\0clk_mac_pll\0clk_uart0_pll\0uart0_frac\0clk_uart1_pll\0uart1_frac\0clk_uart2_pll\0uart2_frac\0reserved\0reserved";
  1671. #clock-cells = < 0x01 >;
  1672. linux,phandle = < 0x67 >;
  1673. phandle = < 0x67 >;
  1674. };
  1675.  
  1676. gate-clk@00d8 {
  1677. compatible = "rockchip,rk3188-gate-clk";
  1678. reg = < 0xd8 0x04 >;
  1679. clocks = < 0x38 0x38 0x19 0x38 0x38 0x38 0x32 0x35 0x4d 0x36 0x1a 0x21 0x1c 0x23 0x24 0x33 >;
  1680. clock-output-names = "reserved\0clk_ddrmon\0clk_gmac\0reserved\0reserved\0reserved\0clk_tsp\0clk_crypto\0clk_tsadc\0clk_spi0\0clk_spdif_pll\0clk_sdmmc0\0spdif_frac\0clk_sdio\0clk_emmc\0clk_wifi";
  1681. #clock-cells = < 0x01 >;
  1682. linux,phandle = < 0x84 >;
  1683. phandle = < 0x84 >;
  1684. };
  1685.  
  1686. gate-clk@00dc {
  1687. compatible = "rockchip,rk3188-gate-clk";
  1688. reg = < 0xdc 0x04 >;
  1689. clocks = < 0x0e 0x38 0x03 0x3a 0x42 0x34 0x31 0x02 0x05 0x38 0x38 0x04 0x38 0x38 0x38 0x38 >;
  1690. clock-output-names = "aclk_iep\0dclk_vop0\0aclk_rkvdec\0clk_vdec_cabac\0clk_vdec_core\0clk_hdcp\0clk_rga\0clk_hdmi_hdcp\0clk_hdmi_cec\0reserved\0reserved\0aclk_vpu\0reserved\0clk_gpu\0reserved\0reserved";
  1691. #clock-cells = < 0x01 >;
  1692. linux,phandle = < 0x95 >;
  1693. phandle = < 0x95 >;
  1694. };
  1695.  
  1696. gate-clk@00e0 {
  1697. compatible = "rockchip,rk3188-gate-clk";
  1698. reg = < 0xe0 0x04 >;
  1699. clocks = < 0x06 0x06 0x44 0x38 0x04 0x03 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 >;
  1700. clock-output-names = "aclk_core\0pclk_dbg\0aclk_gic400\0reserved\0hclk_vpu\0hclk_rkvdec\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved";
  1701. #clock-cells = < 0x01 >;
  1702. linux,phandle = < 0x61 >;
  1703. phandle = < 0x61 >;
  1704. };
  1705.  
  1706. gate-clk@00e4 {
  1707. compatible = "rockchip,rk3188-gate-clk";
  1708. reg = < 0xe4 0x04 >;
  1709. clocks = < 0x20 0x20 0x20 0x4e 0x4e 0x4e 0x4e 0x3b 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 >;
  1710. clock-output-names = "aclk_peri\0hclk_peri\0pclk_peri\0clk_mac_ref\0clk_mac_refout\0clk_mac_rx\0clk_mac_tx\0clk_macphy\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved";
  1711. #clock-cells = < 0x01 >;
  1712. linux,phandle = < 0xa8 >;
  1713. phandle = < 0xa8 >;
  1714. };
  1715.  
  1716. gate-clk@00e8 {
  1717. compatible = "rockchip,rk3188-gate-clk";
  1718. reg = < 0xe8 0x04 >;
  1719. clocks = < 0x0d 0x0d 0x0d 0x4f 0x4f 0x02 0x02 0x02 0x02 0x02 0x02 0x38 0x38 0x4f 0x38 0x38 >;
  1720. clock-output-names = "aclk_bus\0hclk_bus\0pclk_bus\0pclk_bus_pre\0pclk_phy\0clk_timer0\0clk_timer1\0clk_timer2\0clk_timer3\0clk_timer4\0clk_timer5\0reserved\0reserved\0pclk_ddr\0reserved\0reserved";
  1721. #clock-cells = < 0x01 >;
  1722. linux,phandle = < 0x52 >;
  1723. phandle = < 0x52 >;
  1724. };
  1725.  
  1726. gate-clk@00ec {
  1727. compatible = "rockchip,rk3188-gate-clk";
  1728. reg = < 0xec 0x04 >;
  1729. clocks = < 0x50 0x50 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x43 0x0e >;
  1730. clock-output-names = "clk_ddrphy\0clk4x_ddrphy\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0g_aclk_gpu\0g_aclk_gpu_noc";
  1731. #clock-cells = < 0x01 >;
  1732. linux,phandle = < 0x43 >;
  1733. phandle = < 0x43 >;
  1734. };
  1735.  
  1736. gate-clk@00f0 {
  1737. compatible = "rockchip,rk3188-gate-clk";
  1738. reg = < 0xf0 0x04 >;
  1739. clocks = < 0x0d 0x0d 0x0d 0x51 0x52 0x0d 0x43 0x00 0x52 0x0d 0x51 0x51 0x51 0x51 0x51 0x51 0x4f 0x4f 0x4f >;
  1740. clock-output-names = "g_aclk_intmem\0g_intmem_mbist\0g_aclk_dmac_bus\0g_hclk_rom\0g_p_ddrupctl\0g_clk_ddrupctl\0g_p_ddrmon\0g_h_i2s0_8ch\0g_h_i2s1_8ch\0g_h_i2s2_2ch\0g_h_spdif_8ch\0g_h_crypto_mst\0g_h_crypto_slv\0g_p_efuse_1024\0g_p_efuse_256\0g_pclk_i2c0";
  1741. #clock-cells = < 0x01 >;
  1742. linux,phandle = < 0x62 >;
  1743. phandle = < 0x62 >;
  1744. };
  1745.  
  1746. gate-clk@00f4 {
  1747. compatible = "rockchip,rk3188-gate-clk";
  1748. reg = < 0xf4 0x04 >;
  1749. clocks = < 0x4f 0x4f 0x4f 0x38 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f >;
  1750. clock-output-names = "g_pclk_i2c1\0g_pclk_i2c2\0g_pclk_i2c3\0reserved\0g_pclk_timer0\0g_pclk_stimer\0g_pclk_spi0\0g_pclk_rk_pwm\0g_pclk_gpio0\0g_pclk_gpio1\0g_pclk_gpio2\0g_pclk_gpio3\0g_pclk_uart0\0g_pclk_uart1\0g_pclk_uart2\0g_pclk_tsadc";
  1751. #clock-cells = < 0x01 >;
  1752. linux,phandle = < 0x64 >;
  1753. phandle = < 0x64 >;
  1754. };
  1755.  
  1756. gate-clk@00f8 {
  1757. compatible = "rockchip,rk3188-gate-clk";
  1758. reg = < 0xf8 0x04 >;
  1759. clocks = < 0x4f 0x0d 0x52 0x0d 0x52 0x04 0x4f 0x52 0x04 0x4f 0x52 0x04 0x52 0x04 0x52 0x04 0x4f 0x51 0x53 0x38 0x38 0x38 >;
  1760. clock-output-names = "g_pclk_grf\0g_aclk_bus\0g_p_mschniu\0g_p_ddrphy\0g_pclk_cru\0g_p_acodecphy\0g_pclk_sgrf\0g_p_hdmiphy\0g_p_vdacphy\0g_p_phy_noc\0g_pclk_sim\0g_hclk_tsp\0clk_hsadc_tsp\0reserved\0reserved\0reserved";
  1761. #clock-cells = < 0x01 >;
  1762. linux,phandle = < 0x63 >;
  1763. phandle = < 0x63 >;
  1764. };
  1765.  
  1766. gate-clk@00fc {
  1767. compatible = "rockchip,rk3188-gate-clk";
  1768. reg = < 0xfc 0x04 >;
  1769. clocks = < 0x54 0x54 0x54 0x54 0x20 0x55 0x54 0x54 0x54 0x54 0x54 0x38 0x54 0x54 0x54 0x38 >;
  1770. clock-output-names = "g_hclk_sdmmc\0g_hclk_sdio\0g_clk_emmc\0g_clk_nandc\0g_aclk_gmac\0g_pclk_gmac\0g_hclk_host0\0g_h_host0_arb\0g_hclk_host1\0g_h_host1_arb\0g_hclk_host2\0reserved\0g_hclk_otg\0g_hclk_otg_pmu\0g_h_host2_arb\0reserved";
  1771. #clock-cells = < 0x01 >;
  1772. linux,phandle = < 0x99 >;
  1773. phandle = < 0x99 >;
  1774. };
  1775.  
  1776. gate-clk@0100 {
  1777. compatible = "rockchip,rk3188-gate-clk";
  1778. reg = < 0x100 0x04 >;
  1779. clocks = < 0x20 0x54 0x55 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 >;
  1780. clock-output-names = "g_a_peri_noc\0g_h_peri_noc\0g_p_peri_noc\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved";
  1781. #clock-cells = < 0x01 >;
  1782. linux,phandle = < 0x65 >;
  1783. phandle = < 0x65 >;
  1784. };
  1785.  
  1786. gate-clk@0104 {
  1787. compatible = "rockchip,rk3188-gate-clk";
  1788. reg = < 0x104 0x04 >;
  1789. clocks = < 0x56 0x0b 0x57 0x56 0x09 0x57 0x38 0x40 0x57 0x56 0x08 0x57 0x0e 0x3f 0x31 0x40 0x57 0x38 0x38 >;
  1790. clock-output-names = "g_aclk_rga\0g_hclk_rga\0g_aclk_iep\0g_hclk_iep\0reserved\0g_aclk_vop\0g_hclk_vop\0g_h_vio_ahbarbi\0g_h_vio_noc\0g_a_iep_noc\0g_a_hdcp_noc\0g_a_rga_noc\0g_a_vop_noc\0g_h_vop_noc\0reserved\0reserved";
  1791. #clock-cells = < 0x01 >;
  1792. linux,phandle = < 0x56 >;
  1793. phandle = < 0x56 >;
  1794. };
  1795.  
  1796. gate-clk@0108 {
  1797. compatible = "rockchip,rk3188-gate-clk";
  1798. reg = < 0x108 0x04 >;
  1799. clocks = < 0x38 0x38 0x38 0x38 0x38 0x38 0x57 0x57 0x38 0x38 0x3f 0x57 0x57 0x38 0x38 0x38 >;
  1800. clock-output-names = "reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0g_p_hdmi_ctrl\0g_h_vio_h2p\0reserved\0reserved\0g_aclk_hdcp\0g_pclk_hdcp\0g_h_hdcp_mmu\0reserved\0reserved\0reserved";
  1801. #clock-cells = < 0x01 >;
  1802. linux,phandle = < 0x66 >;
  1803. phandle = < 0x66 >;
  1804. };
  1805.  
  1806. gate-clk@010c {
  1807. compatible = "rockchip,rk3188-gate-clk";
  1808. reg = < 0x10c 0x04 >;
  1809. clocks = < 0x38 0x38 0x03 0x58 0x59 0x00 0x59 0x01 0x59 0x02 0x59 0x03 0x38 0x38 0x38 0x38 0x38 0x38 0x38 0x38 >;
  1810. clock-output-names = "g_aclk_vpu\0g_hclk_vpu\0g_a_rkvdec\0g_h_rkvdec\0g_a_vpu_noc\0g_h_vpu_noc\0g_a_rkvdec_noc\0g_h_rkvdec_noc\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved\0reserved";
  1811. #clock-cells = < 0x01 >;
  1812. linux,phandle = < 0x59 >;
  1813. phandle = < 0x59 >;
  1814. };
  1815. };
  1816. };
  1817. };
  1818.  
  1819. dram_timing {
  1820. compatible = "rockchip,dram-timing";
  1821. dram_spd_bin = < 0x15 >;
  1822. sr_idle = < 0x18 >;
  1823. pd_idle = < 0x20 >;
  1824. dram_dll_disb_freq = < 0x12c >;
  1825. phy_dll_disb_freq = < 0x190 >;
  1826. dram_odt_disb_freq = < 0x14d >;
  1827. phy_odt_disb_freq = < 0x14d >;
  1828. ddr3_drv = < 0x00 >;
  1829. ddr3_odt = < 0x40 >;
  1830. lpddr3_drv = < 0x01 >;
  1831. lpddr3_odt = < 0x03 >;
  1832. lpddr2_drv = < 0x01 >;
  1833. phy_ddr3_clk_drv = < 0x12 >;
  1834. phy_ddr3_cmd_drv = < 0x12 >;
  1835. phy_ddr3_dqs_drv = < 0x15 >;
  1836. phy_ddr3_odt = < 0x02 >;
  1837. phy_lp23_clk_drv = < 0x13 >;
  1838. phy_lp23_cmd_drv = < 0x16 >;
  1839. phy_lp23_dqs_drv = < 0x16 >;
  1840. phy_lp3_odt = < 0x02 >;
  1841. linux,phandle = < 0x5e >;
  1842. phandle = < 0x5e >;
  1843. };
  1844.  
  1845. cpus {
  1846. #address-cells = < 0x01 >;
  1847. #size-cells = < 0x00 >;
  1848.  
  1849. cpu@0 {
  1850. device_type = "cpu";
  1851. compatible = "arm,cortex-a7";
  1852. reg = < 0xf00 >;
  1853. };
  1854.  
  1855. cpu@1 {
  1856. device_type = "cpu";
  1857. compatible = "arm,cortex-a7";
  1858. reg = < 0xf01 >;
  1859. };
  1860.  
  1861. cpu@2 {
  1862. device_type = "cpu";
  1863. compatible = "arm,cortex-a7";
  1864. reg = < 0xf02 >;
  1865. };
  1866.  
  1867. cpu@3 {
  1868. device_type = "cpu";
  1869. compatible = "arm,cortex-a7";
  1870. reg = < 0xf03 >;
  1871. };
  1872. };
  1873.  
  1874. psci {
  1875. compatible = "arm,psci";
  1876. method = "smc";
  1877. cpu_suspend = < 0x84000001 >;
  1878. cpu_off = < 0x84000002 >;
  1879. cpu_on = < 0x84000003 >;
  1880. };
  1881.  
  1882. interrupt-controller@32010000 {
  1883. compatible = "arm,cortex-a15-gic";
  1884. interrupt-controller;
  1885. #interrupt-cells = < 0x03 >;
  1886. #address-cells = < 0x00 >;
  1887. reg = < 0x32011000 0x1000 0x32012000 0x1000 >;
  1888. linux,phandle = < 0x01 >;
  1889. phandle = < 0x01 >;
  1890. };
  1891.  
  1892. syscon@10140000 {
  1893. compatible = "rockchip,rk322x-sgrf\0rockchip,sgrf\0syscon";
  1894. reg = < 0x10140000 0x1000 >;
  1895. };
  1896.  
  1897. syscon@11000000 {
  1898. compatible = "rockchip,rk322x-grf\0rockchip,grf\0syscon";
  1899. reg = < 0x11000000 0x1000 >;
  1900. linux,phandle = < 0x5b >;
  1901. phandle = < 0x5b >;
  1902. };
  1903.  
  1904. syscon@110e0000 {
  1905. compatible = "rockchip,rk322x-cru\0rockchip,cru\0syscon";
  1906. reg = < 0x110e0000 0x1000 >;
  1907. linux,phandle = < 0xa7 >;
  1908. phandle = < 0xa7 >;
  1909. };
  1910.  
  1911. syscon@11200000 {
  1912. compatible = "rockchip,rk322x-ddrpctl\0syscon";
  1913. reg = < 0x11200000 0x400 >;
  1914. };
  1915.  
  1916. syscon@31020000 {
  1917. compatible = "rockchip,rk322x-msch\0rockchip,msch\0syscon";
  1918. reg = < 0x31020000 0x3000 >;
  1919. };
  1920.  
  1921. arm-pmu {
  1922. compatible = "arm,cortex-a7-pmu";
  1923. interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 >;
  1924. };
  1925.  
  1926. reset@110e0110 {
  1927. compatible = "rockchip,reset";
  1928. reg = < 0x110e0110 0x20 >;
  1929. rockchip,reset-flag = < 0x01 >;
  1930. #reset-cells = < 0x01 >;
  1931. linux,phandle = < 0x8d >;
  1932. phandle = < 0x8d >;
  1933. };
  1934.  
  1935. timer {
  1936. compatible = "arm,armv7-timer";
  1937. interrupts = < 0x01 0x0d 0xf04 0x01 0x0e 0xf04 >;
  1938. clock-frequency = < 0x16e3600 >;
  1939. };
  1940.  
  1941. timer@110c0000 {
  1942. compatible = "rockchip,timer";
  1943. reg = < 0x110c0000 0x20 >;
  1944. interrupts = < 0x00 0x2b 0x04 >;
  1945. rockchip,broadcast = < 0x01 >;
  1946. };
  1947.  
  1948. fiq-debugger {
  1949. compatible = "rockchip,fiq-debugger";
  1950. rockchip,serial-id = < 0x02 >;
  1951. rockchip,signal-irq = < 0x9f >;
  1952. rockchip,wake-irq = < 0x00 >;
  1953. rockchip,irq-mode-enable = < 0x00 >;
  1954. rockchip,baudrate = < 0x16e360 >;
  1955. pinctrl-names = "default";
  1956. pinctrl-0 = < 0x5a >;
  1957. status = "okay";
  1958. };
  1959.  
  1960. io-domains {
  1961. compatible = "rockchip,rk322x-io-voltage-domain";
  1962. rockchip,grf = < 0x5b >;
  1963. status = "okay";
  1964. vccio1-supply = < 0x5c >;
  1965. vccio2-supply = < 0x5d >;
  1966. vccio4-supply = < 0x5c >;
  1967. };
  1968.  
  1969. dvfs {
  1970.  
  1971. vd_arm {
  1972. regulator_name = "vdd_arm";
  1973.  
  1974. pd_core {
  1975.  
  1976. clk_core {
  1977. operating-points = < 0x639c0 0xe7ef0 0x927c0 0xee098 0xc7380 0xf4240 0xf6180 0x11edd8 0x124f80 0x137478 0x13c680 0x1437c8 >;
  1978. max-volt = < 0x149970 >;
  1979. temp-limit-enable = < 0x01 >;
  1980. target-temp = < 0x5f >;
  1981. min_temp_limit = < 0x927c0 >;
  1982. normal-temp-limit = < 0x03 0x17700 0x06 0x23280 0x09 0x2ee00 0x0f 0x5dc00 >;
  1983. performance-temp-limit = < 0x6e 0xc7380 >;
  1984. status = "okay";
  1985. regu-mode-table = < 0xf6180 0x04 0x00 0x03 >;
  1986. regu-mode-en = < 0x00 >;
  1987. lkg_adjust_volt_en = < 0x01 >;
  1988. channel = < 0x00 >;
  1989. tsadc-ch = < 0x00 >;
  1990. def_table_lkg = < 0x08 >;
  1991. min_adjust_freq = < 0xf6180 >;
  1992. lkg_adjust_volt_table = < 0x14 0xc350 0x3c 0x124f8 >;
  1993. };
  1994. };
  1995. };
  1996.  
  1997. vd_logic {
  1998. regulator_name = "vdd_logic";
  1999.  
  2000. pd_ddr {
  2001.  
  2002. clk_ddr {
  2003. operating-points = < 0x493e0 0x100590 0x927c0 0x100590 0x9e340 0x10c8e0 0xc3500 0x118c30 >;
  2004. lkg_adjust_volt_en = < 0x01 >;
  2005. channel = < 0x02 >;
  2006. def_table_lkg = < 0x05 >;
  2007. min_adjust_freq = < 0x493e0 >;
  2008. lkg_adjust_volt_table = < 0x07 0xc350 0x3c 0x186a0 >;
  2009. temp-limit-enable = < 0x01 >;
  2010. status = "okay";
  2011. freq-table = < 0x01 0xa9ec0 0x10 0xa9ec0 0x10000 0xa9ec0 >;
  2012. };
  2013. };
  2014.  
  2015. pd_gpu {
  2016.  
  2017. clk_gpu {
  2018. operating-points = < 0x30d40 0x100590 0x493e0 0x100590 0x7a120 0x118c30 >;
  2019. temp-limit-enable = < 0x01 >;
  2020. target-temp = < 0x5f >;
  2021. min_temp_limit = < 0x30d40 >;
  2022. normal-temp-limit = < 0x03 0x186a0 >;
  2023. channel = < 0x02 >;
  2024. status = "okay";
  2025. regu-mode-table = < 0x30d40 0x04 0x00 0x03 >;
  2026. regu-mode-en = < 0x00 >;
  2027. };
  2028. };
  2029. };
  2030. };
  2031.  
  2032. rockchip-ion {
  2033. compatible = "rockchip,ion";
  2034. #address-cells = < 0x01 >;
  2035. #size-cells = < 0x00 >;
  2036.  
  2037. system-heap {
  2038. compatible = "rockchip,ion-heap";
  2039. rockchip,ion_heap = < 0x00 >;
  2040. };
  2041. };
  2042.  
  2043. dram {
  2044. compatible = "rockchip,rk322x-dram";
  2045. status = "okay";
  2046. dram_freq = < 0x2ed96880 >;
  2047. rockchip,dram_timing = < 0x5e >;
  2048. };
  2049.  
  2050. clocks-init {
  2051. compatible = "rockchip,clocks-init";
  2052. rockchip,clocks-init-parent = < 0x1e 0x08 0x10 0x08 0x2d 0x08 0x1a 0x08 0x41 0x0b 0x5f 0x0c 0x21 0x0b 0x24 0x0b 0x23 0x0b 0x04 0x0b 0x0c 0x45 0x22 0x48 0x03 0x0b >;
  2053. rockchip,clocks-init-rate = < 0x08 0x47868c00 0x06 0x29b92700 0x0b 0x1dcd6500 0x0d 0x8f0d180 0x51 0x8f0d180 0x4f 0x47868c0 0x20 0x8f0d180 0x54 0x8f0d180 0x55 0x47868c0 0x4e 0x7735940 0x0e 0xee6b280 0x57 0x7735940 0x31 0xee6b280 0x41 0xee6b280 0x04 0x17d7840 0x42 0xee6b280 0x3a 0xee6b280 0x03 0xf42400 0x40 0x17d78400 >;
  2054. };
  2055.  
  2056. clocks-enable {
  2057. compatible = "rockchip,clocks-enable";
  2058. clocks = < 0x07 0x09 0x08 0x0b 0x06 0x60 0x44 0x61 0x02 0x52 0x03 0x43 0x01 0x62 0x05 0x62 0x00 0x62 0x01 0x62 0x02 0x63 0x01 0x62 0x03 0x62 0x04 0x62 0x06 0x64 0x04 0x64 0x05 0x64 0x08 0x63 0x00 0x63 0x04 0x63 0x06 0x63 0x03 0x63 0x09 0x63 0x02 0x65 0x00 0x65 0x01 0x65 0x02 0x56 0x07 0x66 0x07 0x52 0x05 0x52 0x06 0x59 0x04 0x59 0x06 0x59 0x05 0x59 0x07 0x56 0x0b 0x43 0x0f 0x56 0x09 0x56 0x0c 0x56 0x0a 0x56 0x08 0x56 0x0d 0x67 0x03 >;
  2059. };
  2060.  
  2061. serial@11010000 {
  2062. compatible = "rockchip,serial";
  2063. reg = < 0x11010000 0x100 >;
  2064. interrupts = < 0x00 0x37 0x04 >;
  2065. clock-frequency = < 0x16e3600 >;
  2066. clocks = < 0x68 0x64 0x0c >;
  2067. clock-names = "sclk_uart\0pclk_uart";
  2068. reg-shift = < 0x02 >;
  2069. reg-io-width = < 0x04 >;
  2070. dmas = < 0x69 0x02 0x69 0x03 >;
  2071. #dma-cells = < 0x02 >;
  2072. pinctrl-names = "default";
  2073. pinctrl-0 = < 0x6a 0x6b 0x6c >;
  2074. status = "disabled";
  2075. };
  2076.  
  2077. serial@11020000 {
  2078. compatible = "rockchip,serial";
  2079. reg = < 0x11020000 0x100 >;
  2080. interrupts = < 0x00 0x38 0x04 >;
  2081. clock-frequency = < 0x16e3600 >;
  2082. clocks = < 0x6d 0x64 0x0d >;
  2083. clock-names = "sclk_uart\0pclk_uart";
  2084. reg-shift = < 0x02 >;
  2085. reg-io-width = < 0x04 >;
  2086. dmas = < 0x69 0x04 0x69 0x05 >;
  2087. #dma-cells = < 0x02 >;
  2088. pinctrl-names = "default";
  2089. pinctrl-0 = < 0x6e 0x6f >;
  2090. status = "okay";
  2091. dma-names = "!tx\0!rx";
  2092. };
  2093.  
  2094. serial@11030000 {
  2095. compatible = "rockchip,serial";
  2096. reg = < 0x11030000 0x100 >;
  2097. interrupts = < 0x00 0x39 0x04 >;
  2098. clock-frequency = < 0x16e3600 >;
  2099. clocks = < 0x70 0x64 0x0e >;
  2100. clock-names = "sclk_uart\0pclk_uart";
  2101. reg-shift = < 0x02 >;
  2102. reg-io-width = < 0x04 >;
  2103. dmas = < 0x69 0x06 0x69 0x07 >;
  2104. #dma-cells = < 0x02 >;
  2105. pinctrl-names = "default";
  2106. pinctrl-0 = < 0x5a >;
  2107. status = "disabled";
  2108. };
  2109.  
  2110. i2c@11050000 {
  2111. compatible = "rockchip,rk30-i2c";
  2112. reg = < 0x11050000 0x1000 >;
  2113. interrupts = < 0x00 0x24 0x04 >;
  2114. #address-cells = < 0x01 >;
  2115. #size-cells = < 0x00 >;
  2116. pinctrl-names = "default\0gpio\0sleep";
  2117. pinctrl-0 = < 0x71 >;
  2118. pinctrl-1 = < 0x72 >;
  2119. pinctrl-2 = < 0x73 >;
  2120. gpios = < 0x74 0x01 0x01 0x74 0x00 0x01 >;
  2121. clocks = < 0x62 0x0f >;
  2122. rockchip,check-idle = < 0x01 >;
  2123. status = "okay";
  2124. clock-frequency = < 0x30d40 >;
  2125.  
  2126. rtc@51 {
  2127. compatible = "rtc,hym8563";
  2128. reg = < 0x51 >;
  2129. status = "disabled";
  2130. };
  2131.  
  2132. hym8563@51 {
  2133. compatible = "rtc_hym8563";
  2134. reg = < 0x51 >;
  2135. };
  2136. };
  2137.  
  2138. i2c@11060000 {
  2139. compatible = "rockchip,rk30-i2c";
  2140. reg = < 0x11060000 0x1000 >;
  2141. interrupts = < 0x00 0x25 0x04 >;
  2142. #address-cells = < 0x01 >;
  2143. #size-cells = < 0x00 >;
  2144. pinctrl-names = "default\0gpio\0sleep";
  2145. pinctrl-0 = < 0x75 >;
  2146. pinctrl-1 = < 0x76 >;
  2147. pinctrl-2 = < 0x77 >;
  2148. gpios = < 0x74 0x03 0x01 0x74 0x02 0x01 >;
  2149. clocks = < 0x64 0x00 >;
  2150. rockchip,check-idle = < 0x01 >;
  2151. status = "disabled";
  2152.  
  2153. nau8540@1c {
  2154. compatible = "nuvoton,nau8540";
  2155. reg = < 0x1c >;
  2156. linux,phandle = < 0xc0 >;
  2157. phandle = < 0xc0 >;
  2158. };
  2159.  
  2160. nau8540@1d {
  2161. compatible = "nuvoton,nau8540";
  2162. reg = < 0x1d >;
  2163. };
  2164. };
  2165.  
  2166. i2c@11070000 {
  2167. compatible = "rockchip,rk30-i2c";
  2168. reg = < 0x11070000 0x1000 >;
  2169. interrupts = < 0x00 0x26 0x04 >;
  2170. #address-cells = < 0x01 >;
  2171. #size-cells = < 0x00 >;
  2172. pinctrl-names = "default\0gpio\0sleep";
  2173. pinctrl-0 = < 0x78 >;
  2174. pinctrl-1 = < 0x79 >;
  2175. pinctrl-2 = < 0x7a >;
  2176. gpios = < 0x7b 0x14 0x01 0x7b 0x15 0x01 >;
  2177. clocks = < 0x64 0x01 >;
  2178. rockchip,check-idle = < 0x01 >;
  2179. status = "disabled";
  2180. };
  2181.  
  2182. i2c@11080000 {
  2183. compatible = "rockchip,rk30-i2c";
  2184. reg = < 0x11080000 0x1000 >;
  2185. interrupts = < 0x00 0x27 0x04 >;
  2186. #address-cells = < 0x01 >;
  2187. #size-cells = < 0x00 >;
  2188. pinctrl-names = "default\0gpio\0sleep";
  2189. pinctrl-0 = < 0x7c >;
  2190. pinctrl-1 = < 0x7d >;
  2191. pinctrl-2 = < 0x7e >;
  2192. gpios = < 0x74 0x07 0x01 0x74 0x06 0x01 >;
  2193. clocks = < 0x64 0x02 >;
  2194. rockchip,check-idle = < 0x01 >;
  2195. status = "disabled";
  2196. };
  2197.  
  2198. spi@11090000 {
  2199. compatible = "rockchip,rockchip-spi";
  2200. reg = < 0x11090000 0x1000 >;
  2201. interrupts = < 0x00 0x31 0x04 >;
  2202. #address-cells = < 0x01 >;
  2203. #size-cells = < 0x00 >;
  2204. pinctrl-names = "default";
  2205. pinctrl-0 = < 0x7f 0x80 0x81 0x82 0x83 >;
  2206. rockchip,spi-src-clk = < 0x00 >;
  2207. num-cs = < 0x02 >;
  2208. clocks = < 0x84 0x09 0x64 0x06 >;
  2209. clock-names = "spi\0pclk_spi0";
  2210. status = "disabled";
  2211. max-freq = < 0x2dc6c00 >;
  2212.  
  2213. spi_test@00 {
  2214. compatible = "rockchip,spi_test_bus0_cs0";
  2215. reg = < 0x00 >;
  2216. spi-max-frequency = < 0xb71b00 >;
  2217. poll_mode = < 0x00 >;
  2218. type = < 0x00 >;
  2219. };
  2220.  
  2221. spi_test@01 {
  2222. compatible = "rockchip,spi_test_bus0_cs1";
  2223. reg = < 0x01 >;
  2224. spi-max-frequency = < 0xb71b00 >;
  2225. spi-cpha;
  2226. spi-cpol;
  2227. poll_mode = < 0x00 >;
  2228. type = < 0x00 >;
  2229. };
  2230. };
  2231.  
  2232. wdt@110a0000 {
  2233. compatible = "rockchip,watch dog";
  2234. reg = < 0x110a0000 0x100 >;
  2235. clocks = < 0x52 0x03 >;
  2236. clock-names = "pclk_wdt";
  2237. interrupts = < 0x00 0x28 0x04 >;
  2238. rockchip,irq = < 0x01 >;
  2239. rockchip,timeout = < 0x3c >;
  2240. rockchip,atboot = < 0x01 >;
  2241. rockchip,debug = < 0x00 >;
  2242. status = "disabled";
  2243. };
  2244.  
  2245. amba {
  2246. #address-cells = < 0x01 >;
  2247. #size-cells = < 0x01 >;
  2248. compatible = "arm,amba-bus";
  2249. interrupt-parent = < 0x01 >;
  2250. ranges;
  2251.  
  2252. pdma@110f0000 {
  2253. compatible = "arm,pl330\0arm,primecell";
  2254. reg = < 0x110f0000 0x4000 >;
  2255. clocks = < 0x62 0x02 >;
  2256. clock-names = "apb_pclk";
  2257. interrupts = < 0x00 0x00 0x04 0x00 0x01 0x04 >;
  2258. #dma-cells = < 0x01 >;
  2259. linux,phandle = < 0x69 >;
  2260. phandle = < 0x69 >;
  2261. };
  2262. };
  2263.  
  2264. crypto@100a0000 {
  2265. compatible = "rockchip-crypto";
  2266. reg = < 0x100a0000 0x10000 >;
  2267. interrupts = < 0x00 0x1e 0x04 >;
  2268. interrupt-names = "irq_crypto";
  2269. clocks = < 0x35 0x62 0x0c 0x62 0x0b >;
  2270. clock-names = "clk_crypto\0hclk_crypto\0aclk_crypto";
  2271. status = "disabled";
  2272. };
  2273.  
  2274. i2s0@100c0000 {
  2275. compatible = "rockchip-i2s";
  2276. reg = < 0x100c0000 0x1000 >;
  2277. i2s-id = < 0x00 >;
  2278. clocks = < 0x49 0x62 0x07 >;
  2279. clock-names = "i2s_clk\0i2s_hclk";
  2280. interrupts = < 0x00 0x1a 0x04 >;
  2281. dmas = < 0x69 0x0b 0x69 0x0c >;
  2282. #dma-cells = < 0x02 >;
  2283. dma-names = "tx\0rx";
  2284. status = "okay";
  2285. linux,phandle = < 0xbf >;
  2286. phandle = < 0xbf >;
  2287. };
  2288.  
  2289. i2s1@100b0000 {
  2290. compatible = "rockchip-i2s";
  2291. reg = < 0x100b0000 0x1000 >;
  2292. i2s-id = < 0x01 >;
  2293. clocks = < 0x15 0x4b 0x62 0x08 >;
  2294. clock-names = "i2s_clk\0i2s_mclk\0i2s_hclk";
  2295. interrupts = < 0x00 0x1b 0x04 >;
  2296. dmas = < 0x69 0x0e 0x69 0x0f >;
  2297. #dma-cells = < 0x02 >;
  2298. dma-names = "tx\0rx";
  2299. status = "okay";
  2300. linux,phandle = < 0xbb >;
  2301. phandle = < 0xbb >;
  2302. };
  2303.  
  2304. i2s2@100e0000 {
  2305. compatible = "rockchip-i2s";
  2306. reg = < 0x100e0000 0x1000 >;
  2307. i2s-id = < 0x02 >;
  2308. clocks = < 0x4a 0x62 0x09 >;
  2309. clock-names = "i2s_clk\0i2s_hclk";
  2310. interrupts = < 0x00 0x1c 0x04 >;
  2311. dmas = < 0x69 0x00 0x69 0x01 >;
  2312. #dma-cells = < 0x02 >;
  2313. dma-names = "tx\0rx";
  2314. pinctrl-names = "default\0sleep";
  2315. pinctrl-0 = < 0x85 0x86 0x87 0x88 >;
  2316. pinctrl-1 = < 0x89 >;
  2317. status = "disabled";
  2318. };
  2319.  
  2320. spdif@100d0000 {
  2321. compatible = "rockchip-spdif";
  2322. reg = < 0x100d0000 0x1000 >;
  2323. clocks = < 0x8a 0x62 0x0a >;
  2324. clock-names = "spdif_mclk\0spdif_hclk";
  2325. interrupts = < 0x00 0x1d 0x04 >;
  2326. dmas = < 0x69 0x0a >;
  2327. #dma-cells = < 0x01 >;
  2328. dma-names = "tx";
  2329. pinctrl-names = "default";
  2330. pinctrl-0 = < 0x8b >;
  2331. status = "okay";
  2332. linux,phandle = < 0xbd >;
  2333. phandle = < 0xbd >;
  2334. };
  2335.  
  2336. codec@12010000 {
  2337. compatible = "rockchip,rk322x-codec";
  2338. reg = < 0x12010000 0x1000 >;
  2339. clocks = < 0x63 0x05 >;
  2340. clock-names = "g_pclk_acodec";
  2341. spk_ctl_io = < 0x8c 0x03 0x00 >;
  2342. status = "okay";
  2343. spk_depop_time = < 0x64 >;
  2344. linux,phandle = < 0xba >;
  2345. phandle = < 0xba >;
  2346. };
  2347.  
  2348. codec-spdif {
  2349. compatible = "hdmi-spdif";
  2350. status = "okay";
  2351. linux,phandle = < 0xbc >;
  2352. phandle = < 0xbc >;
  2353. };
  2354.  
  2355. codec-hdmi-i2s {
  2356. compatible = "hdmi-i2s";
  2357. status = "okay";
  2358. linux,phandle = < 0xbe >;
  2359. phandle = < 0xbe >;
  2360. };
  2361.  
  2362. tsadc@11150000 {
  2363. compatible = "rockchip,rk322x-tsadc";
  2364. reg = < 0x11150000 0x100 >;
  2365. interrupts = < 0x00 0x3a 0x04 >;
  2366. clock-frequency = < 0x8000 >;
  2367. clocks = < 0x4d 0x64 0x0f >;
  2368. clock-names = "tsadc\0pclk_tsadc";
  2369. resets = < 0x8d 0x57 >;
  2370. reset-names = "tsadc-apb";
  2371. #io-channel-cells = < 0x01 >;
  2372. io-channel-ranges;
  2373. pinctrl-names = "default";
  2374. pinctrl-0 = < 0x8e >;
  2375. tsadc-ht-temp = < 0x78 >;
  2376. tsadc-ht-reset-cru = < 0x01 >;
  2377. tsadc-ht-pull-gpio = < 0x00 >;
  2378. status = "okay";
  2379. };
  2380.  
  2381. gpu {
  2382. compatible = "arm,mali400";
  2383. reg = < 0x20001000 0x200 0x20000000 0x100 0x20003000 0x100 0x20008000 0x1100 0x20004000 0x100 0x2000a000 0x1100 0x20005000 0x100 >;
  2384. reg-names = "Mali_L2\0Mali_GP\0Mali_GP_MMU\0Mali_PP0\0Mali_PP0_MMU\0Mali_PP1\0Mali_PP1_MMU";
  2385. interrupts = < 0x00 0x06 0x04 0x00 0x05 0x04 0x00 0x04 0x04 0x00 0x05 0x04 0x00 0x04 0x04 0x00 0x05 0x04 >;
  2386. interrupt-names = "Mali_GP_IRQ\0Mali_GP_MMU_IRQ\0Mali_PP0_IRQ\0Mali_PP0_MMU_IRQ\0Mali_PP1_IRQ\0Mali_PP1_MMU_IRQ";
  2387. };
  2388.  
  2389. fb {
  2390. compatible = "rockchip,rk-fb";
  2391. rockchip,disp-mode = < 0x00 >;
  2392. rockchip,disp-policy = < 0x01 >;
  2393. rockchip,uboot-logo-on = < 0x01 >;
  2394. };
  2395.  
  2396. rk_screen {
  2397. compatible = "rockchip,screen";
  2398. display-timings = < 0x8f >;
  2399. };
  2400.  
  2401. pwm@110b0000 {
  2402. compatible = "rockchip,rk-pwm";
  2403. reg = < 0x110b0000 0x10 >;
  2404. interrupts = < 0x00 0x32 0x04 >;
  2405. #pwm-cells = < 0x02 >;
  2406. pinctrl-names = "default";
  2407. pinctrl-0 = < 0x90 >;
  2408. clocks = < 0x64 0x07 >;
  2409. clock-names = "pclk_pwm";
  2410. status = "disabled";
  2411. };
  2412.  
  2413. pwm@110b0010 {
  2414. compatible = "rockchip,rk-pwm";
  2415. reg = < 0x110b0010 0x10 >;
  2416. interrupts = < 0x00 0x32 0x04 >;
  2417. #pwm-cells = < 0x02 >;
  2418. pinctrl-names = "default";
  2419. pinctrl-0 = < 0x91 >;
  2420. clocks = < 0x64 0x07 >;
  2421. clock-names = "pclk_pwm";
  2422. status = "okay";
  2423. linux,phandle = < 0xb8 >;
  2424. phandle = < 0xb8 >;
  2425. };
  2426.  
  2427. pwm@110b0020 {
  2428. compatible = "rockchip,rk-pwm";
  2429. reg = < 0x110b0020 0x10 >;
  2430. interrupts = < 0x00 0x32 0x04 >;
  2431. #pwm-cells = < 0x02 >;
  2432. pinctrl-names = "default";
  2433. pinctrl-0 = < 0x92 >;
  2434. clocks = < 0x64 0x07 >;
  2435. clock-names = "pclk_pwm";
  2436. status = "okay";
  2437. linux,phandle = < 0xb9 >;
  2438. phandle = < 0xb9 >;
  2439. };
  2440.  
  2441. pwm@110b0030 {
  2442. compatible = "rockchip,remotectl-pwm";
  2443. reg = < 0x110b0030 0x10 >;
  2444. interrupts = < 0x00 0x32 0x04 >;
  2445. #pwm-cells = < 0x02 >;
  2446. pinctrl-names = "default";
  2447. pinctrl-0 = < 0x93 >;
  2448. clocks = < 0x64 0x07 >;
  2449. clock-names = "pclk_pwm";
  2450. status = "okay";
  2451. remote_pwm_id = < 0x03 >;
  2452. handle_cpu_id = < 0x01 >;
  2453.  
  2454. ir_key1 {
  2455. rockchip,usercode = < 0x4040 >;
  2456. rockchip,key_table = < 0xb2 0x74 0xbc 0x71 0xac 0x12d 0xa4 0x12c 0xa8 0x68 0xab 0x6d 0xe3 0x7a 0xe1 0x7b 0xe0 0x78 0xea 0x79 0xe5 0x184 0xbd 0x9e 0xf4 0x67 0xef 0x69 0xf2 0xe8 0xee 0x6a 0xf1 0x6c 0xba 0x77 0xbb 0x96 0xfe 0x02 0xfd 0x03 0xfc 0x04 0xfb 0x05 0xfa 0x06 0xf9 0x07 0xf8 0x08 0xf7 0x09 0xf6 0x0a 0xf0 0x3d 0xff 0x0b 0xf3 0x0e >;
  2457. };
  2458.  
  2459. ir_key2 {
  2460. rockchip,usercode = < 0xff00 >;
  2461. rockchip,key_table = < 0xeb 0x74 0xb9 0x71 0xf6 0x15 0xe2 0x16 0xe0 0x17 0xaa 0x19 0xf2 0x18 0xaf 0x1a 0xed 0x1b 0xa6 0x2b 0xfc 0x1d 0xf7 0x1e 0xf9 0x67 0xbb 0x6c 0xb8 0x69 0xbf 0x6a 0xf8 0x1c 0xe8 0x1f 0xb5 0x9e 0xac 0x21 0xe1 0x22 0xad 0x20 0xfe 0x23 0xf5 0x25 0xba 0x24 0xe4 0x26 0xea 0x27 0xee 0x28 0xe6 0x29 0xae 0x72 0xfd 0x73 >;
  2462. };
  2463.  
  2464. ir_key3 {
  2465. rockchip,usercode = < 0x1dcc >;
  2466. rockchip,key_table = < 0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x7a 0xf5 0x7b 0xb3 0x184 0xbe 0x02 0xba 0x03 0xb2 0x04 0xbd 0x05 0xb9 0x06 0xb1 0x07 0xbc 0x08 0xb8 0x09 0xb0 0x0a 0xb6 0x0b 0xb5 0x0e 0xfe 0x99 0xfa 0x98 0xf6 0x97 0xf2 0x12b 0xf7 0x12b 0xe4 0x96 >;
  2467. };
  2468.  
  2469. ir_key4 {
  2470. rockchip,usercode = < 0xfe01 >;
  2471. rockchip,key_table = < 0xbf 0x74 0xff 0x184 0xbc 0x96 0xf0 0x12b 0xef 0x6d 0xe7 0x68 0xee 0x66 0xe6 0x9e 0xe9 0x67 0xe5 0x6c 0xec 0xe8 0xae 0x69 0xaf 0x6a 0xb3 0x8b 0xb1 0x02 0xf2 0x03 0xf3 0x04 0xb5 0x05 0xf6 0x06 0xf7 0x07 0xb9 0x08 0xfa 0x09 0xfb 0x0a 0xbe 0x71 0xfe 0x0b 0xed 0x04 0xbd 0x0e >;
  2472. };
  2473.  
  2474. ir_key5 {
  2475. rockchip,usercode = < 0xbd02 >;
  2476. rockchip,key_table = < 0xb9 0x96 0xb8 0x96 0xb7 0x96 0xb6 0x96 0x27 0x96 0xa6 0x96 0xa5 0x96 0x44 0x96 0xa9 0x80 0x34 0x7a 0xa8 0x7b 0xa7 0x12a 0xac 0x78 0xad 0x79 0xdc 0x77 0xab 0x129 0x6a 0x184 0x3a 0x12a 0x3e 0x6a 0x66 0x69 0x35 0x67 0x2d 0x6c 0x31 0xe8 0x2f 0x9e 0x29 0x46 0x65 0x130 0x32 0x131 0x63 0x8b 0x76 0x71 0x73 0x6d 0xf2 0x68 0x6d 0x02 0x6c 0x03 0x33 0x04 0x71 0x05 0x70 0x06 0x37 0x07 0x75 0x08 0x74 0x09 0x3b 0x0a 0x78 0x0b 0x26 0x0e 0x7d 0x8b >;
  2477. };
  2478.  
  2479. ir_key6 {
  2480. rockchip,usercode = < 0xdf00 >;
  2481. rockchip,key_table = < 0xe3 0x74 0xf7 0x71 0xaa 0x12a 0xa1 0x96 0xae 0x12b 0xae 0x128 0xa5 0x79 0xad 0x78 0xa2 0x7a 0xa3 0x7b 0xfe 0x127 0xa0 0x8c 0xe6 0x77 0xa7 0x80 0xe7 0x8b 0xe8 0x126 0xe5 0x67 0xb8 0x69 0xf9 0xe8 0xf8 0x6a 0xb7 0x6c 0xb6 0x97 0xf5 0x9e 0xb4 0x73 0xb0 0x72 0xfc 0x66 0xbd 0x184 0xf6 0x124 0xfa 0x125 0xab 0x02 0xe9 0x03 0xea 0x04 0xaf 0x05 0xed 0x06 0xee 0x07 0xb3 0x08 0xf1 0x09 0xf2 0x0a 0xf3 0x0b 0xbe 0x34 0xef 0x0e >;
  2482. };
  2483.  
  2484. ir_key7 {
  2485. rockchip,usercode = < 0xf708 >;
  2486. rockchip,key_table = < 0xfd 0x69 0xe1 0x6a 0xe4 0x67 0xe5 0xe8 0xe6 0x6c 0xe2 0x9e 0xf4 0x74 0xfc 0x73 0xfe 0x66 0xe0 0x72 0xf2 0xb9 0xee 0xb7 0xa6 0x71 >;
  2487. };
  2488.  
  2489. ir_key8 {
  2490. rockchip,usercode = < 0xbf00 >;
  2491. rockchip,key_table = < 0xa6 0x74 0xe6 0x71 0xbd 0x125 0xbf 0x121 0xff 0x126 0xfc 0x127 0xec 0x66 0xa7 0x0f 0xf9 0x67 0xe9 0x6c 0xa5 0x69 0xe4 0x6a 0xe5 0xe8 0xba 0x8b 0xfa 0x184 0xb2 0x12b 0xae 0x96 0xe8 0x122 0xb7 0x123 0xf2 0x68 0xee 0x6d 0xad 0x02 0xaf 0x03 0xef 0x04 0xa9 0x05 0xab 0x06 0xeb 0x07 0xb1 0x08 0xb3 0x09 0xf3 0x0a 0xf0 0x0b 0xf7 0x0e 0xf4 0x1d2 0xf1 0x1d0 0xaa 0x1d7 0xf8 0x1dc 0xe7 0x1db >;
  2492. };
  2493.  
  2494. ir_key9 {
  2495. rockchip,usercode = < 0x7f80 >;
  2496. rockchip,key_table = < 0xae 0x74 0xb2 0x71 0xf6 0x12a 0xee 0x12b 0xab 0x68 0xb0 0x6d 0xa9 0x7a 0x42 0x7b 0x44 0x78 0xb1 0x79 0xac 0x184 0xe4 0x9e 0xd9 0x67 0xda 0x69 0xf2 0xe8 0xd8 0x6a 0xd7 0x6c 0xb6 0x77 0xad 0x8b 0xce 0x02 0xcd 0x03 0xcc 0x04 0xcb 0x05 0xca 0x06 0xc9 0x07 0xc8 0x08 0xc7 0x09 0xc6 0x0a 0xa7 0x3d 0xcf 0x0b 0xbb 0x0e >;
  2497. };
  2498.  
  2499. ir_key10 {
  2500. rockchip,usercode = < 0xef00 >;
  2501. rockchip,key_table = < 0xff 0x74 0xfd 0x66 0xfc 0x8b 0xfe 0x67 0xe0 0x6c 0xe5 0x69 0xe4 0x6a 0xfa 0xe8 0xf8 0x68 0xfb 0x6d 0xf9 0x71 0xe2 0x9e 0xf3 0x02 0xf2 0x03 0xf1 0x04 0xf0 0x05 0xef 0x06 0xee 0x07 0xed 0x08 0xec 0x09 0xeb 0x0a 0xea 0x0b 0xe9 0x0e 0xe8 0x96 >;
  2502. };
  2503. };
  2504.  
  2505. vpu_service@20020000 {
  2506. compatible = "vpu_service";
  2507. rockchip,grf = < 0x5b >;
  2508. iommu_enabled = < 0x01 >;
  2509. reg = < 0x20020000 0x800 >;
  2510. interrupts = < 0x00 0x09 0x04 0x00 0x0b 0x04 >;
  2511. interrupt-names = "irq_dec\0irq_enc";
  2512. clocks = < 0x04 0x94 >;
  2513. clock-names = "aclk_vcodec\0hclk_vcodec";
  2514. resets = < 0x8d 0x71 0x8d 0x70 >;
  2515. reset-names = "video_h\0video_a";
  2516. dev_mode = < 0x00 >;
  2517. status = "okay";
  2518. };
  2519.  
  2520. rkvdec@20030000 {
  2521. compatible = "rockchip,rkvdec";
  2522. rockchip,grf = < 0x5b >;
  2523. iommu_enabled = < 0x01 >;
  2524. reg = < 0x20030000 0x400 >;
  2525. interrupts = < 0x00 0x07 0x04 >;
  2526. interrupt-names = "irq_dec";
  2527. clocks = < 0x03 0x58 0x3a 0x42 >;
  2528. clock-names = "aclk_vcodec\0hclk_vcodec\0clk_cabac\0clk_core";
  2529. resets = < 0x8d 0x78 0x8d 0x76 >;
  2530. reset-names = "video_h\0video_a";
  2531. dev_mode = < 0x02 >;
  2532. status = "okay";
  2533. };
  2534.  
  2535. vop@20050000 {
  2536. compatible = "rockchip,rk322x-lcdc";
  2537. rockchip,prop = < 0x01 >;
  2538. rockchip,cabc_mode = < 0x00 >;
  2539. rockchip,pwr18 = < 0x00 >;
  2540. rockchip,iommu-enabled = < 0x01 >;
  2541. reg = < 0x20050000 0x2000 >;
  2542. interrupts = < 0x00 0x20 0x04 >;
  2543. clocks = < 0x56 0x05 0x5f 0x56 0x06 0x56 0x0c 0x56 0x0d >;
  2544. clock-names = "aclk_vop\0dclk_vop\0hclk_vop\0aclk_vop_noc\0hclk_vop_noc";
  2545. };
  2546.  
  2547. rga@20060000 {
  2548. compatible = "rockchip,rga2";
  2549. reg = < 0x20060000 0x1000 >;
  2550. interrupts = < 0x00 0x21 0x04 >;
  2551. clocks = < 0x56 0x00 0x56 0x01 0x31 >;
  2552. clock-names = "aclk_rga\0hclk_rga\0pd_rga";
  2553. };
  2554.  
  2555. iep@20070000 {
  2556. compatible = "rockchip,iep";
  2557. iommu_enabled = < 0x01 >;
  2558. reg = < 0x20070000 0x800 >;
  2559. interrupts = < 0x00 0x1f 0x04 >;
  2560. clocks = < 0x56 0x02 0x56 0x03 >;
  2561. clock-names = "aclk_iep\0hclk_iep";
  2562. version = < 0x03 >;
  2563. status = "okay";
  2564. };
  2565.  
  2566. vop_mmu {
  2567. dbgname = "vop";
  2568. compatible = "rockchip,vop_mmu";
  2569. reg = < 0x20053f00 0x100 >;
  2570. interrupts = < 0x00 0x20 0x04 >;
  2571. interrupt-names = "vop_mmu";
  2572. };
  2573.  
  2574. vpu_mmu {
  2575. dbgname = "vpu";
  2576. compatible = "rockchip,vpu_mmu";
  2577. reg = < 0x20020800 0x100 >;
  2578. interrupts = < 0x00 0x0a 0x04 >;
  2579. interrupt-names = "vpu_mmu";
  2580. };
  2581.  
  2582. iep_mmu {
  2583. dbgname = "iep";
  2584. compatible = "rockchip,iep_mmu";
  2585. reg = < 0x20070800 0x100 >;
  2586. interrupts = < 0x00 0x1f 0x04 >;
  2587. interrupt-names = "iep_mmu";
  2588. };
  2589.  
  2590. vdec_mmu {
  2591. dbgname = "vdec";
  2592. compatible = "rockchip,vdec_mmu";
  2593. reg = < 0x20030480 0x40 0x200304c0 0x40 >;
  2594. interrupts = < 0x00 0x08 0x04 >;
  2595. interrupt-names = "vdec_mmu";
  2596. };
  2597.  
  2598. hdmi@200a0000 {
  2599. compatible = "rockchip,rk322x-hdmi";
  2600. reg = < 0x200a0000 0x20000 0x12030000 0x10000 >;
  2601. interrupts = < 0x00 0x23 0x04 0x00 0x47 0x04 >;
  2602. clocks = < 0x95 0x07 0x66 0x06 0x63 0x07 0x05 >;
  2603. clock-names = "hdcp_clk_hdmi\0pclk_hdmi\0pclk_hdmi_phy\0cec_clk_hdmi";
  2604. pinctrl-names = "default\0gpio";
  2605. pinctrl-0 = < 0x96 0x97 0x98 >;
  2606. pinctrl-1 = < 0x7d >;
  2607. resets = < 0x8d 0x60 >;
  2608. reset-names = "hdmi";
  2609. rockchip,grf = < 0x5b >;
  2610. rockchip,hdmi_audio_source = < 0x00 >;
  2611. rockchip,hdcp_enable = < 0x00 >;
  2612. rockchip,cec_enable = < 0x00 >;
  2613. status = "okay";
  2614. rockchip,phy_table = < 0x9d5b340 0x00 0x00 0x1f 0x1f 0x1f 0x1f 0xd693a40 0x00 0x00 0x1f 0x1f 0x1f 0x1f 0x1443fd00 0x01 0x00 0x1f 0x1f 0x1f 0x1f 0x2367b880 0x01 0x00 0x1f 0x1f 0x1f 0x1f >;
  2615. };
  2616.  
  2617. hdmi_hdcp2@20090000 {
  2618. compatible = "rockchip,rk322x-hdmi-hdcp2";
  2619. reg = < 0x20090000 0x10000 >;
  2620. interrupts = < 0x00 0x22 0x04 >;
  2621. clocks = < 0x56 0x0a 0x66 0x0c 0x66 0x0b 0x66 0x0a 0x34 >;
  2622. clock-names = "aclk_noc_hdcp2\0hclk_hdcp2_mmu\0pclk_hdcp2\0aclk_hdcp2\0hdcp2_clk_hdmi";
  2623. status = "disabled";
  2624. };
  2625.  
  2626. tve {
  2627. compatible = "rockchip,rk322x-tve";
  2628. reg = < 0x20053e00 0x100 0x12020000 0x10000 >;
  2629. clocks = < 0x63 0x08 >;
  2630. clock-names = "pclk_vdac";
  2631. saturation = < 0x305b46 >;
  2632. brightcontrast = < 0x9900 >;
  2633. adjtiming = < 0xd6c00880 >;
  2634. lumafilter0 = < 0x2ff0001 >;
  2635. lumafilter1 = < 0xf40200fe >;
  2636. lumafilter2 = < 0xf332d910 >;
  2637. daclevel = < 0x15 >;
  2638. dac1level = < 0x07 >;
  2639. status = "okay";
  2640. };
  2641.  
  2642. rksdmmc@30020000 {
  2643. compatible = "rockchip,rk_mmc\0rockchip,rk322x-sdmmc";
  2644. reg = < 0x30020000 0x10000 >;
  2645. interrupts = < 0x00 0x0e 0x04 >;
  2646. #address-cells = < 0x01 >;
  2647. #size-cells = < 0x00 >;
  2648. clocks = < 0x24 0x99 0x02 >;
  2649. clock-names = "clk_mmc\0hclk_mmc";
  2650. num-slots = < 0x01 >;
  2651. fifo-depth = < 0x100 >;
  2652. bus-width = < 0x08 >;
  2653. tune_regsbase = < 0x1d8 >;
  2654. resets = < 0x8d 0x53 >;
  2655. reset-names = "mmc_ahb_reset";
  2656. clock-frequency = < 0x2faf080 >;
  2657. clock-freq-min-max = < 0x61a80 0x2faf080 >;
  2658. supports-highspeed;
  2659. supports-emmc;
  2660. bootpart-no-access;
  2661. supports-DDR_MODE;
  2662. ignore-pm-notify;
  2663. keep-power-in-suspend;
  2664. status = "okay";
  2665. };
  2666.  
  2667. rksdmmc@30000000 {
  2668. compatible = "rockchip,rk_mmc\0rockchip,rk322x-sdmmc";
  2669. reg = < 0x30000000 0x10000 >;
  2670. interrupts = < 0x00 0x0c 0x04 >;
  2671. #address-cells = < 0x01 >;
  2672. #size-cells = < 0x00 >;
  2673. pinctrl-names = "default\0idle";
  2674. pinctrl-0 = < 0x9a 0x9b 0x9c 0x9d 0x9e >;
  2675. pinctrl-1 = < 0x9f >;
  2676. cd-gpios = < 0x8c 0x11 0x00 >;
  2677. clocks = < 0x21 0x99 0x00 >;
  2678. clock-names = "clk_mmc\0hclk_mmc";
  2679. num-slots = < 0x01 >;
  2680. fifo-depth = < 0x100 >;
  2681. bus-width = < 0x04 >;
  2682. resets = < 0x8d 0x51 >;
  2683. reset-names = "mmc_ahb_reset";
  2684. clock-frequency = < 0x23c3460 >;
  2685. clock-freq-min-max = < 0x61a80 0x23c3460 >;
  2686. supports-highspeed;
  2687. supports-sd;
  2688. broken-cd;
  2689. card-detect-delay = < 0xc8 >;
  2690. ignore-pm-notify;
  2691. keep-power-in-suspend;
  2692. power-inverted;
  2693. status = "okay";
  2694. };
  2695.  
  2696. rksdmmc@30010000 {
  2697. compatible = "rockchip,rk_mmc\0rockchip,rk322x-sdmmc";
  2698. reg = < 0x30010000 0x10000 >;
  2699. interrupts = < 0x00 0x0d 0x04 >;
  2700. #address-cells = < 0x01 >;
  2701. #size-cells = < 0x00 >;
  2702. pinctrl-names = "default\0idle";
  2703. pinctrl-0 = < 0xa0 0xa1 0xa2 >;
  2704. pinctrl-1 = < 0xa3 >;
  2705. clocks = < 0x23 0x99 0x01 >;
  2706. clock-names = "clk_mmc\0hclk_mmc";
  2707. num-slots = < 0x01 >;
  2708. fifo-depth = < 0x100 >;
  2709. bus-width = < 0x04 >;
  2710. tune_regsbase = < 0x1c8 >;
  2711. resets = < 0x8d 0x52 >;
  2712. reset-names = "mmc_ahb_reset";
  2713. clock-frequency = < 0x23c3460 >;
  2714. clock-freq-min-max = < 0x30d40 0x23c3460 >;
  2715. supports-highspeed;
  2716. supports-sdio;
  2717. ignore-pm-notify;
  2718. keep-power-in-suspend;
  2719. cap-sdio-irq;
  2720. status = "disabled";
  2721. };
  2722.  
  2723. nandc@30030000 {
  2724. compatible = "rockchip,rk-nandc";
  2725. reg = < 0x30030000 0x4000 >;
  2726. interrupts = < 0x00 0x0f 0x04 >;
  2727. nandc_id = < 0x00 >;
  2728. clocks = < 0x0f 0x67 0x00 0x99 0x03 >;
  2729. clock-names = "clk_nandc\0g_clk_nandc\0hclk_nandc";
  2730. status = "okay";
  2731. };
  2732.  
  2733. phy {
  2734. compatible = "rockchip,rk322x-usb-phy";
  2735. rockchip,grf = < 0x5b >;
  2736. #address-cells = < 0x01 >;
  2737. #size-cells = < 0x00 >;
  2738.  
  2739. usb-phy0 {
  2740. #phy-cells = < 0x00 >;
  2741. reg = < 0x764 >;
  2742. linux,phandle = < 0xa4 >;
  2743. phandle = < 0xa4 >;
  2744. };
  2745.  
  2746. usb-phy1 {
  2747. #phy-cells = < 0x00 >;
  2748. reg = < 0x800 >;
  2749. linux,phandle = < 0xa5 >;
  2750. phandle = < 0xa5 >;
  2751. };
  2752.  
  2753. usb-phy2 {
  2754. #phy-cells = < 0x00 >;
  2755. reg = < 0x804 >;
  2756. linux,phandle = < 0xa6 >;
  2757. phandle = < 0xa6 >;
  2758. };
  2759. };
  2760.  
  2761. otg@30040000 {
  2762. compatible = "rockchip,rk322x_usb20_otg";
  2763. reg = < 0x30040000 0x40000 >;
  2764. interrupts = < 0x00 0x17 0x04 >;
  2765. clocks = < 0x67 0x05 0x99 0x0c 0x99 0x0d >;
  2766. clock-names = "clk_usbphy0\0hclk_otg\0hclk_otg_pmu";
  2767. resets = < 0x8d 0x45 0x8d 0x67 0x8d 0x46 >;
  2768. reset-names = "otg_ahb\0otg_phy\0otg_controller";
  2769. rockchip,usb-mode = < 0x01 >;
  2770. };
  2771.  
  2772. ehci0@30080000 {
  2773. compatible = "generic-ehci";
  2774. reg = < 0x30080000 0x20000 >;
  2775. interrupts = < 0x00 0x10 0x04 >;
  2776. clocks = < 0x67 0x05 0x99 0x06 0x99 0x07 >;
  2777. clock-names = "clk_usbphy0\0hclk_host0\0hclk_host0_arb";
  2778. phys = < 0xa4 >;
  2779. phy-names = "usb";
  2780. resets = < 0x8d 0x47 0x8d 0x68 0x8d 0x48 >;
  2781. reset-names = "host_ahb\0host_phy\0host_controller";
  2782. };
  2783.  
  2784. ohci0@300a0000 {
  2785. compatible = "generic-ohci";
  2786. reg = < 0x300a0000 0x20000 >;
  2787. interrupts = < 0x00 0x11 0x04 >;
  2788. };
  2789.  
  2790. ehci1@300c0000 {
  2791. compatible = "generic-ehci";
  2792. reg = < 0x300c0000 0x20000 >;
  2793. interrupts = < 0x00 0x13 0x04 >;
  2794. clocks = < 0x67 0x06 0x99 0x08 0x99 0x09 >;
  2795. clock-names = "clk_usbphy1\0hclk_host1\0hclk_host1_arb";
  2796. phys = < 0xa5 >;
  2797. phy-names = "usb";
  2798. resets = < 0x8d 0x49 0x8d 0x69 0x8d 0x4a >;
  2799. reset-names = "host_ahb\0host_phy\0host_controller";
  2800. };
  2801.  
  2802. ohci1@300e0000 {
  2803. compatible = "generic-ohci";
  2804. reg = < 0x300e0000 0x20000 >;
  2805. interrupts = < 0x00 0x14 0x04 >;
  2806. };
  2807.  
  2808. ehci2@30100000 {
  2809. compatible = "generic-ehci";
  2810. reg = < 0x30100000 0x20000 >;
  2811. interrupts = < 0x00 0x42 0x04 >;
  2812. clocks = < 0x67 0x06 0x99 0x0a 0x99 0x0e >;
  2813. clock-names = "clk_usbphy1\0hclk_host2\0hck_host2_arb";
  2814. phys = < 0xa6 >;
  2815. phy-names = "usb";
  2816. resets = < 0x8d 0x4b 0x8d 0x6a 0x8d 0x4c >;
  2817. reset-names = "host_ahb\0host_phy\0host_controller";
  2818. };
  2819.  
  2820. ohci2@30120000 {
  2821. compatible = "generic-ohci";
  2822. reg = < 0x30120000 0x20000 >;
  2823. interrupts = < 0x00 0x43 0x04 >;
  2824. };
  2825.  
  2826. eth@30200000 {
  2827. compatible = "rockchip,rk322x-gmac";
  2828. reg = < 0x30200000 0x10000 >;
  2829. rockchip,cru = < 0xa7 >;
  2830. rockchip,grf = < 0x5b >;
  2831. interrupts = < 0x00 0x18 0x04 >;
  2832. interrupt-names = "macirq";
  2833. clocks = < 0x4e 0xa8 0x05 0xa8 0x06 0xa8 0x03 0xa8 0x04 0x99 0x04 0x99 0x05 >;
  2834. clock-names = "clk_mac\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
  2835. phy-mode = "rmii";
  2836. pinctrl-names = "default";
  2837. pinctrl-0 = < 0xa9 >;
  2838. status = "disabled";
  2839. link-gpio = < 0x7b 0x0e 0x00 >;
  2840. led-gpio = < 0x7b 0x08 0x00 >;
  2841. clock_in_out = "output";
  2842. tx_delay = < 0x26 >;
  2843. rx_delay = < 0x11 >;
  2844. phy-type = "internal";
  2845. };
  2846.  
  2847. rockchip_suspend {
  2848. rockchip,ctrbits = < 0x11806 >;
  2849. };
  2850.  
  2851. pinctrl {
  2852. compatible = "rockchip,rk322x-pinctrl";
  2853. rockchip,grf = < 0x5b >;
  2854. #address-cells = < 0x01 >;
  2855. #size-cells = < 0x01 >;
  2856. ranges;
  2857.  
  2858. gpio0@11110000 {
  2859. compatible = "rockchip,gpio-bank";
  2860. reg = < 0x11110000 0x100 >;
  2861. interrupts = < 0x00 0x33 0x04 >;
  2862. clocks = < 0x64 0x09 >;
  2863. gpio-controller;
  2864. #gpio-cells = < 0x02 >;
  2865. interrupt-controller;
  2866. #interrupt-cells = < 0x02 >;
  2867. linux,phandle = < 0x74 >;
  2868. phandle = < 0x74 >;
  2869. };
  2870.  
  2871. gpio1@11120000 {
  2872. compatible = "rockchip,gpio-bank";
  2873. reg = < 0x11120000 0x100 >;
  2874. interrupts = < 0x00 0x34 0x04 >;
  2875. clocks = < 0x64 0x09 >;
  2876. gpio-controller;
  2877. #gpio-cells = < 0x02 >;
  2878. interrupt-controller;
  2879. #interrupt-cells = < 0x02 >;
  2880. linux,phandle = < 0x8c >;
  2881. phandle = < 0x8c >;
  2882. };
  2883.  
  2884. gpio2@11130000 {
  2885. compatible = "rockchip,gpio-bank";
  2886. reg = < 0x11130000 0x100 >;
  2887. interrupts = < 0x00 0x35 0x04 >;
  2888. clocks = < 0x64 0x0a >;
  2889. gpio-controller;
  2890. #gpio-cells = < 0x02 >;
  2891. interrupt-controller;
  2892. #interrupt-cells = < 0x02 >;
  2893. linux,phandle = < 0x7b >;
  2894. phandle = < 0x7b >;
  2895. };
  2896.  
  2897. gpio3@11140000 {
  2898. compatible = "rockchip,gpio-bank";
  2899. reg = < 0x11140000 0x100 >;
  2900. interrupts = < 0x00 0x36 0x04 >;
  2901. clocks = < 0x64 0x0b >;
  2902. gpio-controller;
  2903. #gpio-cells = < 0x02 >;
  2904. interrupt-controller;
  2905. #interrupt-cells = < 0x02 >;
  2906. linux,phandle = < 0xb4 >;
  2907. phandle = < 0xb4 >;
  2908. };
  2909.  
  2910. pcfg-pull-up {
  2911. bias-pull-up;
  2912. linux,phandle = < 0xac >;
  2913. phandle = < 0xac >;
  2914. };
  2915.  
  2916. pcfg-pull-down {
  2917. bias-pull-down;
  2918. linux,phandle = < 0xb2 >;
  2919. phandle = < 0xb2 >;
  2920. };
  2921.  
  2922. pcfg-pull-none {
  2923. bias-disable;
  2924. linux,phandle = < 0xaa >;
  2925. phandle = < 0xaa >;
  2926. };
  2927.  
  2928. pcfg-pull-none-drv-8ma {
  2929. drive-strength = < 0x08 >;
  2930. linux,phandle = < 0xaf >;
  2931. phandle = < 0xaf >;
  2932. };
  2933.  
  2934. pcfg-pull-none-drv-12ma {
  2935. drive-strength = < 0x0c >;
  2936. linux,phandle = < 0xb1 >;
  2937. phandle = < 0xb1 >;
  2938. };
  2939.  
  2940. pcfg-pull-up-drv-8ma {
  2941. bias-pull-up;
  2942. drive-strength = < 0x08 >;
  2943. linux,phandle = < 0xb0 >;
  2944. phandle = < 0xb0 >;
  2945. };
  2946.  
  2947. pcfg-pull-none-drv-4ma {
  2948. drive-strength = < 0x04 >;
  2949. linux,phandle = < 0xad >;
  2950. phandle = < 0xad >;
  2951. };
  2952.  
  2953. pcfg-pull-up-drv-4ma {
  2954. bias-pull-up;
  2955. drive-strength = < 0x04 >;
  2956. linux,phandle = < 0xae >;
  2957. phandle = < 0xae >;
  2958. };
  2959.  
  2960. pcfg-pull-down-drv-12ma {
  2961. bias-pull-down;
  2962. drive-strength = < 0x0c >;
  2963. };
  2964.  
  2965. pcfg-output-high {
  2966. output-high;
  2967. };
  2968.  
  2969. pcfg-output-low {
  2970. output-low;
  2971. };
  2972.  
  2973. pcfg-input-high {
  2974. bias-pull-up;
  2975. input-enable;
  2976. linux,phandle = < 0xab >;
  2977. phandle = < 0xab >;
  2978. };
  2979.  
  2980. i2c0 {
  2981.  
  2982. i2c0-xfer {
  2983. rockchip,pins = < 0x00 0x00 0x01 0xaa 0x00 0x01 0x01 0xaa >;
  2984. linux,phandle = < 0x71 >;
  2985. phandle = < 0x71 >;
  2986. };
  2987.  
  2988. i2c0-gpio {
  2989. rockchip,pins = < 0x00 0x00 0x00 0xaa 0x00 0x01 0x00 0xaa >;
  2990. linux,phandle = < 0x72 >;
  2991. phandle = < 0x72 >;
  2992. };
  2993.  
  2994. i2c0-sleep {
  2995. rockchip,pins = < 0x00 0x00 0x00 0xab 0x00 0x01 0x00 0xab >;
  2996. linux,phandle = < 0x73 >;
  2997. phandle = < 0x73 >;
  2998. };
  2999. };
  3000.  
  3001. i2c1 {
  3002.  
  3003. i2c1-xfer {
  3004. rockchip,pins = < 0x00 0x02 0x01 0xaa 0x00 0x03 0x01 0xaa >;
  3005. linux,phandle = < 0x75 >;
  3006. phandle = < 0x75 >;
  3007. };
  3008.  
  3009. i2c1-gpio {
  3010. rockchip,pins = < 0x00 0x02 0x00 0xaa 0x00 0x03 0x00 0xaa >;
  3011. linux,phandle = < 0x76 >;
  3012. phandle = < 0x76 >;
  3013. };
  3014.  
  3015. i2c1-sleep {
  3016. rockchip,pins = < 0x00 0x02 0x00 0xab 0x00 0x03 0x00 0xab >;
  3017. linux,phandle = < 0x77 >;
  3018. phandle = < 0x77 >;
  3019. };
  3020. };
  3021.  
  3022. i2c2 {
  3023.  
  3024. i2c2-xfer {
  3025. rockchip,pins = < 0x02 0x15 0x01 0xaa 0x02 0x14 0x01 0xaa >;
  3026. linux,phandle = < 0x78 >;
  3027. phandle = < 0x78 >;
  3028. };
  3029.  
  3030. i2c2-gpio {
  3031. rockchip,pins = < 0x02 0x15 0x00 0xaa 0x02 0x14 0x00 0xaa >;
  3032. linux,phandle = < 0x79 >;
  3033. phandle = < 0x79 >;
  3034. };
  3035.  
  3036. i2c2-sleep {
  3037. rockchip,pins = < 0x02 0x15 0x00 0xab 0x02 0x14 0x00 0xab >;
  3038. linux,phandle = < 0x7a >;
  3039. phandle = < 0x7a >;
  3040. };
  3041. };
  3042.  
  3043. i2c3 {
  3044.  
  3045. i2c3-xfer {
  3046. rockchip,pins = < 0x00 0x06 0x01 0xaa 0x00 0x07 0x01 0xaa >;
  3047. linux,phandle = < 0x7c >;
  3048. phandle = < 0x7c >;
  3049. };
  3050.  
  3051. i2c3-gpio {
  3052. rockchip,pins = < 0x00 0x06 0x00 0xaa 0x00 0x07 0x00 0xaa >;
  3053. linux,phandle = < 0x7d >;
  3054. phandle = < 0x7d >;
  3055. };
  3056.  
  3057. i2c3-sleep {
  3058. rockchip,pins = < 0x00 0x06 0x00 0xab 0x00 0x07 0x00 0xab >;
  3059. linux,phandle = < 0x7e >;
  3060. phandle = < 0x7e >;
  3061. };
  3062. };
  3063.  
  3064. uart0 {
  3065.  
  3066. uart0-xfer {
  3067. rockchip,pins = < 0x02 0x1a 0x01 0xac 0x02 0x1b 0x01 0xaa >;
  3068. linux,phandle = < 0x6a >;
  3069. phandle = < 0x6a >;
  3070. };
  3071.  
  3072. uart0-cts {
  3073. rockchip,pins = < 0x02 0x1d 0x01 0xaa >;
  3074. linux,phandle = < 0x6b >;
  3075. phandle = < 0x6b >;
  3076. };
  3077.  
  3078. uart0-rts {
  3079. rockchip,pins = < 0x00 0x11 0x01 0xaa >;
  3080. linux,phandle = < 0x6c >;
  3081. phandle = < 0x6c >;
  3082. };
  3083.  
  3084. uart0-rts-gpio {
  3085. rockchip,pins = < 0x00 0x11 0x00 0xaa >;
  3086. };
  3087. };
  3088.  
  3089. uart1 {
  3090.  
  3091. uart1-xfer {
  3092. rockchip,pins = < 0x01 0x0a 0x01 0xac 0x01 0x09 0x01 0xaa >;
  3093. };
  3094.  
  3095. uart1-cts {
  3096. rockchip,pins = < 0x01 0x08 0x01 0xaa >;
  3097. };
  3098.  
  3099. uart1-rts {
  3100. rockchip,pins = < 0x01 0x0b 0x01 0xaa >;
  3101. };
  3102.  
  3103. uart1-rts-gpio {
  3104. rockchip,pins = < 0x01 0x0b 0x00 0xaa >;
  3105. };
  3106. };
  3107.  
  3108. uart11 {
  3109.  
  3110. uart11-xfer {
  3111. rockchip,pins = < 0x03 0x0e 0x01 0xac 0x03 0x0d 0x01 0xaa >;
  3112. linux,phandle = < 0x6e >;
  3113. phandle = < 0x6e >;
  3114. };
  3115.  
  3116. uart11-cts {
  3117. rockchip,pins = < 0x03 0x07 0x01 0xaa >;
  3118. linux,phandle = < 0x6f >;
  3119. phandle = < 0x6f >;
  3120. };
  3121.  
  3122. uart11-rts {
  3123. rockchip,pins = < 0x03 0x06 0x01 0xaa >;
  3124. linux,phandle = < 0xb5 >;
  3125. phandle = < 0xb5 >;
  3126. };
  3127.  
  3128. uart11-rts-gpio {
  3129. rockchip,pins = < 0x03 0x06 0x00 0xaa >;
  3130. linux,phandle = < 0xb6 >;
  3131. phandle = < 0xb6 >;
  3132. };
  3133. };
  3134.  
  3135. uart2 {
  3136.  
  3137. uart2-xfer {
  3138. rockchip,pins = < 0x01 0x12 0x02 0xac 0x01 0x13 0x02 0xaa >;
  3139. };
  3140.  
  3141. uart2-cts {
  3142. rockchip,pins = < 0x00 0x19 0x01 0xaa >;
  3143. };
  3144.  
  3145. uart2-rts {
  3146. rockchip,pins = < 0x00 0x18 0x01 0xaa >;
  3147. };
  3148. };
  3149.  
  3150. uart21 {
  3151.  
  3152. uart21-xfer {
  3153. rockchip,pins = < 0x01 0x0a 0x02 0xac 0x01 0x09 0x02 0xaa >;
  3154. linux,phandle = < 0x5a >;
  3155. phandle = < 0x5a >;
  3156. };
  3157. };
  3158.  
  3159. spi0 {
  3160.  
  3161. spi0-clk {
  3162. rockchip,pins = < 0x00 0x09 0x02 0xac >;
  3163. linux,phandle = < 0x7f >;
  3164. phandle = < 0x7f >;
  3165. };
  3166.  
  3167. spi0-cs0 {
  3168. rockchip,pins = < 0x00 0x0e 0x02 0xac >;
  3169. linux,phandle = < 0x82 >;
  3170. phandle = < 0x82 >;
  3171. };
  3172.  
  3173. spi0-tx {
  3174. rockchip,pins = < 0x00 0x0b 0x02 0xac >;
  3175. linux,phandle = < 0x80 >;
  3176. phandle = < 0x80 >;
  3177. };
  3178.  
  3179. spi0-rx {
  3180. rockchip,pins = < 0x00 0x0d 0x02 0xac >;
  3181. linux,phandle = < 0x81 >;
  3182. phandle = < 0x81 >;
  3183. };
  3184.  
  3185. spi0-cs1 {
  3186. rockchip,pins = < 0x01 0x0c 0x01 0xac >;
  3187. linux,phandle = < 0x83 >;
  3188. phandle = < 0x83 >;
  3189. };
  3190. };
  3191.  
  3192. spi1 {
  3193.  
  3194. spi1-clk {
  3195. rockchip,pins = < 0x00 0x17 0x02 0xac >;
  3196. };
  3197.  
  3198. spi1-cs0 {
  3199. rockchip,pins = < 0x02 0x02 0x02 0xac >;
  3200. };
  3201.  
  3202. spi1-rx {
  3203. rockchip,pins = < 0x02 0x00 0x02 0xac >;
  3204. };
  3205.  
  3206. spi1-tx {
  3207. rockchip,pins = < 0x02 0x01 0x02 0xac >;
  3208. };
  3209.  
  3210. spi1-cs1 {
  3211. rockchip,pins = < 0x02 0x03 0x02 0xac >;
  3212. };
  3213. };
  3214.  
  3215. i2s {
  3216.  
  3217. i2s-mclk {
  3218. rockchip,pins = < 0x00 0x08 0x01 0xaa >;
  3219. };
  3220.  
  3221. i2s-sclk {
  3222. rockchip,pins = < 0x00 0x09 0x01 0xaa >;
  3223. };
  3224.  
  3225. i2s-lrckrx {
  3226. rockchip,pins = < 0x00 0x0b 0x01 0xaa >;
  3227. };
  3228.  
  3229. i2s-lrcktx {
  3230. rockchip,pins = < 0x00 0x0c 0x01 0xaa >;
  3231. };
  3232.  
  3233. i2s-sdi {
  3234. rockchip,pins = < 0x00 0x0e 0x01 0xaa >;
  3235. };
  3236.  
  3237. i2s-sdo0 {
  3238. rockchip,pins = < 0x00 0x0d 0x01 0xaa >;
  3239. };
  3240.  
  3241. i2s-sdo1 {
  3242. rockchip,pins = < 0x01 0x02 0x02 0xaa >;
  3243. };
  3244.  
  3245. i2s-sdo2 {
  3246. rockchip,pins = < 0x01 0x04 0x02 0xaa >;
  3247. };
  3248.  
  3249. i2s-sdo3 {
  3250. rockchip,pins = < 0x01 0x05 0x02 0xaa >;
  3251. };
  3252.  
  3253. i2s-sleep {
  3254. rockchip,pins = < 0x00 0x08 0x00 0xab 0x00 0x09 0x00 0xab 0x00 0x0b 0x00 0xab 0x00 0x0c 0x00 0xab 0x00 0x0e 0x00 0xab 0x00 0x0d 0x00 0xab 0x01 0x02 0x00 0xab 0x01 0x04 0x00 0xab 0x01 0x05 0x00 0xab >;
  3255. };
  3256. };
  3257.  
  3258. pcm {
  3259.  
  3260. pcm-rx {
  3261. rockchip,pins = < 0x00 0x1a 0x02 0xaa >;
  3262. linux,phandle = < 0x85 >;
  3263. phandle = < 0x85 >;
  3264. };
  3265.  
  3266. pcm-tx {
  3267. rockchip,pins = < 0x00 0x1b 0x02 0xaa >;
  3268. linux,phandle = < 0x86 >;
  3269. phandle = < 0x86 >;
  3270. };
  3271.  
  3272. pcm-clk {
  3273. rockchip,pins = < 0x03 0x0b 0x01 0xaa >;
  3274. linux,phandle = < 0x87 >;
  3275. phandle = < 0x87 >;
  3276. };
  3277.  
  3278. pcm-sync {
  3279. rockchip,pins = < 0x03 0x0c 0x01 0xaa >;
  3280. linux,phandle = < 0x88 >;
  3281. phandle = < 0x88 >;
  3282. };
  3283.  
  3284. pcm-sleep {
  3285. rockchip,pins = < 0x00 0x1a 0x00 0xab 0x00 0x1b 0x00 0xab 0x03 0x0b 0x00 0xab 0x03 0x0c 0x00 0xab >;
  3286. linux,phandle = < 0x89 >;
  3287. phandle = < 0x89 >;
  3288. };
  3289. };
  3290.  
  3291. spdif0 {
  3292.  
  3293. spdif0-tx {
  3294. rockchip,pins = < 0x03 0x1b 0x01 0xaa >;
  3295. };
  3296. };
  3297.  
  3298. spdif1 {
  3299.  
  3300. spdif1-tx {
  3301. rockchip,pins = < 0x03 0x1f 0x02 0xaa >;
  3302. linux,phandle = < 0x8b >;
  3303. phandle = < 0x8b >;
  3304. };
  3305. };
  3306.  
  3307. sdmmc {
  3308.  
  3309. sdmmc-clk {
  3310. rockchip,pins = < 0x01 0x10 0x01 0xad >;
  3311. linux,phandle = < 0x9a >;
  3312. phandle = < 0x9a >;
  3313. };
  3314.  
  3315. sdmmc-cmd {
  3316. rockchip,pins = < 0x01 0x0f 0x01 0xae >;
  3317. linux,phandle = < 0x9b >;
  3318. phandle = < 0x9b >;
  3319. };
  3320.  
  3321. sdmmc-dectn {
  3322. rockchip,pins = < 0x01 0x11 0x01 0xae >;
  3323. linux,phandle = < 0x9c >;
  3324. phandle = < 0x9c >;
  3325. };
  3326.  
  3327. sdmmc-wrprt {
  3328. rockchip,pins = < 0x01 0x07 0x02 0xae >;
  3329. };
  3330.  
  3331. sdmmc-pwren {
  3332. rockchip,pins = < 0x01 0x0e 0x01 0xae >;
  3333. linux,phandle = < 0x9e >;
  3334. phandle = < 0x9e >;
  3335. };
  3336.  
  3337. sdmmc-bus1 {
  3338. rockchip,pins = < 0x01 0x12 0x01 0xae >;
  3339. };
  3340.  
  3341. sdmmc-bus4 {
  3342. rockchip,pins = < 0x01 0x12 0x01 0xae 0x01 0x13 0x01 0xae 0x01 0x14 0x01 0xae 0x01 0x15 0x01 0xae >;
  3343. linux,phandle = < 0x9d >;
  3344. phandle = < 0x9d >;
  3345. };
  3346.  
  3347. sdmmc-gpio {
  3348. rockchip,pins = < 0x01 0x10 0x00 0xae 0x01 0x0f 0x00 0xae 0x01 0x11 0x00 0xae 0x01 0x0e 0x00 0xae 0x01 0x12 0x00 0xae 0x01 0x13 0x00 0xae 0x01 0x14 0x00 0xae 0x01 0x15 0x00 0xae >;
  3349. linux,phandle = < 0x9f >;
  3350. phandle = < 0x9f >;
  3351. };
  3352. };
  3353.  
  3354. sdio {
  3355.  
  3356. sdio-bus1 {
  3357. rockchip,pins = < 0x01 0x01 0x01 0xae >;
  3358. };
  3359.  
  3360. sdio-bus4 {
  3361. rockchip,pins = < 0x01 0x01 0x01 0xae 0x01 0x02 0x01 0xae 0x01 0x04 0x01 0xae 0x01 0x05 0x01 0xae >;
  3362. };
  3363.  
  3364. sdio-cmd {
  3365. rockchip,pins = < 0x00 0x03 0x02 0xae >;
  3366. };
  3367.  
  3368. sdio-clk {
  3369. rockchip,pins = < 0x01 0x00 0x01 0xad >;
  3370. };
  3371.  
  3372. sdio-pwren {
  3373. rockchip,pins = < 0x00 0x1e 0x01 0xac >;
  3374. };
  3375.  
  3376. sdio-gpio {
  3377. rockchip,pins = < 0x00 0x03 0x00 0xae 0x01 0x00 0x00 0xae 0x00 0x1e 0x00 0xae 0x01 0x01 0x00 0xae 0x01 0x02 0x00 0xae 0x01 0x03 0x00 0xae 0x01 0x04 0x00 0xae >;
  3378. };
  3379. };
  3380.  
  3381. sdio1 {
  3382.  
  3383. sdio1-bus1 {
  3384. rockchip,pins = < 0x03 0x02 0x01 0xae >;
  3385. };
  3386.  
  3387. sdio1-bus4 {
  3388. rockchip,pins = < 0x03 0x02 0x01 0xae 0x03 0x03 0x01 0xae 0x03 0x04 0x01 0xae 0x03 0x05 0x01 0xae >;
  3389. linux,phandle = < 0xa2 >;
  3390. phandle = < 0xa2 >;
  3391. };
  3392.  
  3393. sdio1-cmd {
  3394. rockchip,pins = < 0x03 0x01 0x01 0xae >;
  3395. linux,phandle = < 0xa0 >;
  3396. phandle = < 0xa0 >;
  3397. };
  3398.  
  3399. sdio1-clk {
  3400. rockchip,pins = < 0x03 0x00 0x01 0xad >;
  3401. linux,phandle = < 0xa1 >;
  3402. phandle = < 0xa1 >;
  3403. };
  3404.  
  3405. sdio1-gpio {
  3406. rockchip,pins = < 0x03 0x03 0x00 0xae 0x03 0x00 0x00 0xae 0x03 0x01 0x00 0xae 0x03 0x02 0x00 0xae 0x03 0x03 0x00 0xae 0x03 0x04 0x00 0xae >;
  3407. linux,phandle = < 0xa3 >;
  3408. phandle = < 0xa3 >;
  3409. };
  3410. };
  3411.  
  3412. emmc {
  3413.  
  3414. emmc-clk {
  3415. rockchip,pins = < 0x02 0x07 0x02 0xaf >;
  3416. };
  3417.  
  3418. emmc-cmd {
  3419. rockchip,pins = < 0x01 0x16 0x02 0xb0 >;
  3420. };
  3421.  
  3422. emmc-pwren {
  3423. rockchip,pins = < 0x02 0x05 0x02 0xaa >;
  3424. };
  3425.  
  3426. emmc_rstnout {
  3427. rockchip,pins = < 0x01 0x17 0x02 0xaa >;
  3428. };
  3429.  
  3430. emmc-bus1 {
  3431. rockchip,pins = < 0x01 0x18 0x02 0xb0 >;
  3432. };
  3433.  
  3434. emmc-bus4 {
  3435. rockchip,pins = < 0x01 0x18 0x02 0xb0 0x01 0x19 0x02 0xb0 0x01 0x1a 0x02 0xb0 0x01 0x1b 0x02 0xb0 >;
  3436. };
  3437.  
  3438. emmc-bus8 {
  3439. rockchip,pins = < 0x01 0x18 0x02 0xb0 0x01 0x19 0x02 0xb0 0x01 0x1a 0x02 0xb0 0x01 0x1b 0x02 0xb0 0x01 0x1c 0x02 0xb0 0x01 0x1d 0x02 0xb0 0x01 0x1e 0x02 0xb0 0x01 0x1f 0x02 0xb0 >;
  3440. };
  3441. };
  3442.  
  3443. emmc1 {
  3444.  
  3445. emmc1-clk {
  3446. rockchip,pins = < 0x02 0x07 0x02 0xaf >;
  3447. };
  3448.  
  3449. emmc1-cmd {
  3450. rockchip,pins = < 0x02 0x04 0x02 0xb0 >;
  3451. };
  3452.  
  3453. emmc1-pwren {
  3454. rockchip,pins = < 0x02 0x05 0x02 0xaa >;
  3455. };
  3456.  
  3457. emmc1_rstnout {
  3458. rockchip,pins = < 0x01 0x17 0x02 0xaa >;
  3459. };
  3460.  
  3461. emmc1-bus1 {
  3462. rockchip,pins = < 0x01 0x18 0x02 0xb0 >;
  3463. };
  3464.  
  3465. emmc1-bus4 {
  3466. rockchip,pins = < 0x01 0x18 0x02 0xb0 0x01 0x19 0x02 0xb0 0x01 0x1a 0x02 0xb0 0x01 0x1b 0x02 0xb0 >;
  3467. };
  3468.  
  3469. emmc1-bus8 {
  3470. rockchip,pins = < 0x01 0x18 0x02 0xb0 0x01 0x19 0x02 0xb0 0x01 0x1a 0x02 0xb0 0x01 0x1b 0x02 0xb0 0x01 0x1c 0x02 0xb0 0x01 0x1d 0x02 0xb0 0x01 0x1e 0x02 0xb0 0x01 0x1f 0x02 0xb0 >;
  3471. };
  3472. };
  3473.  
  3474. pwm0 {
  3475.  
  3476. pwm0-pin {
  3477. rockchip,pins = < 0x00 0x1a 0x01 0xaa >;
  3478. };
  3479. };
  3480.  
  3481. pwm01 {
  3482.  
  3483. pwm01-pin {
  3484. rockchip,pins = < 0x03 0x15 0x01 0xaa >;
  3485. linux,phandle = < 0x90 >;
  3486. phandle = < 0x90 >;
  3487. };
  3488. };
  3489.  
  3490. pwm1 {
  3491.  
  3492. pwm1-pin {
  3493. rockchip,pins = < 0x00 0x1b 0x01 0xaa >;
  3494. };
  3495. };
  3496.  
  3497. pwm11 {
  3498.  
  3499. pwm11-pin {
  3500. rockchip,pins = < 0x00 0x1e 0x02 0xaa >;
  3501. linux,phandle = < 0x91 >;
  3502. phandle = < 0x91 >;
  3503. };
  3504. };
  3505.  
  3506. pwm2 {
  3507.  
  3508. pwm2-pin {
  3509. rockchip,pins = < 0x00 0x1c 0x01 0xaa >;
  3510. };
  3511. };
  3512.  
  3513. pwm21 {
  3514.  
  3515. pwm21-pin {
  3516. rockchip,pins = < 0x01 0x0c 0x02 0xaa >;
  3517. linux,phandle = < 0x92 >;
  3518. phandle = < 0x92 >;
  3519. };
  3520. };
  3521.  
  3522. pwmir {
  3523.  
  3524. pwmir-pin {
  3525. rockchip,pins = < 0x03 0x1a 0x01 0xaa >;
  3526. };
  3527. };
  3528.  
  3529. pwmir1 {
  3530.  
  3531. pwmir1-pin {
  3532. rockchip,pins = < 0x01 0x0b 0x02 0xaa >;
  3533. linux,phandle = < 0x93 >;
  3534. phandle = < 0x93 >;
  3535. };
  3536. };
  3537.  
  3538. gmac {
  3539.  
  3540. rgmii-pins {
  3541. rockchip,pins = < 0x02 0x0e 0x01 0xaa 0x02 0x0c 0x01 0xaa 0x02 0x19 0x01 0xaa 0x02 0x13 0x01 0xb1 0x02 0x12 0x01 0xb1 0x02 0x16 0x01 0xb1 0x02 0x17 0x01 0xb1 0x02 0x09 0x01 0xb1 0x02 0x0d 0x01 0xb1 0x02 0x11 0x01 0xaa 0x02 0x10 0x01 0xaa 0x02 0x15 0x02 0xaa 0x02 0x14 0x02 0xaa 0x02 0x0b 0x01 0xaa 0x02 0x08 0x01 0xaa >;
  3542. };
  3543.  
  3544. rmii-pins {
  3545. rockchip,pins = < 0x02 0x0e 0x01 0xaa 0x02 0x0c 0x01 0xaa 0x02 0x19 0x01 0xaa 0x02 0x13 0x01 0xb1 0x02 0x12 0x01 0xb1 0x02 0x0d 0x01 0xb1 0x02 0x11 0x01 0xaa 0x02 0x10 0x01 0xaa 0x02 0x08 0x01 0xaa 0x02 0x0f 0x01 0xaa >;
  3546. };
  3547.  
  3548. phy-pins {
  3549. rockchip,pins = < 0x02 0x0e 0x02 0xaa 0x02 0x08 0x02 0xaa >;
  3550. linux,phandle = < 0xa9 >;
  3551. phandle = < 0xa9 >;
  3552. };
  3553. };
  3554.  
  3555. tsadc_pin {
  3556.  
  3557. tsadc-int {
  3558. rockchip,pins = < 0x00 0x18 0x02 0xaa >;
  3559. };
  3560.  
  3561. tsadc-gpio {
  3562. rockchip,pins = < 0x00 0x18 0x00 0xaa >;
  3563. linux,phandle = < 0x8e >;
  3564. phandle = < 0x8e >;
  3565. };
  3566. };
  3567.  
  3568. hdmi_pin {
  3569.  
  3570. hdmi-cec {
  3571. rockchip,pins = < 0x00 0x14 0x01 0xaa >;
  3572. linux,phandle = < 0x96 >;
  3573. phandle = < 0x96 >;
  3574. };
  3575.  
  3576. hdmi-hpd {
  3577. rockchip,pins = < 0x00 0x0f 0x01 0xb2 >;
  3578. linux,phandle = < 0x98 >;
  3579. phandle = < 0x98 >;
  3580. };
  3581. };
  3582.  
  3583. hdmi_i2c {
  3584.  
  3585. hdmii2c-xfer {
  3586. rockchip,pins = < 0x00 0x06 0x02 0xaa 0x00 0x07 0x02 0xaa >;
  3587. linux,phandle = < 0x97 >;
  3588. phandle = < 0x97 >;
  3589. };
  3590. };
  3591.  
  3592. rk_4g {
  3593.  
  3594. mcu-pin {
  3595. rockchip,pins = < 0x03 0x14 0x00 0xb0 0x01 0x00 0x00 0xb0 >;
  3596. linux,phandle = < 0xb7 >;
  3597. phandle = < 0xb7 >;
  3598. };
  3599. };
  3600. };
  3601.  
  3602. power_ctr {
  3603. };
  3604.  
  3605. display-timings {
  3606. native-mode = < 0xb3 >;
  3607. linux,phandle = < 0x8f >;
  3608. phandle = < 0x8f >;
  3609.  
  3610. timing0 {
  3611. screen-type = < 0x01 >;
  3612. out-face = < 0x00 >;
  3613. color-mode = < 0x02 >;
  3614. clock-frequency = < 0x46cf710 >;
  3615. hactive = < 0x500 >;
  3616. vactive = < 0x2d0 >;
  3617. hback-porch = < 0xdc >;
  3618. hfront-porch = < 0x6e >;
  3619. vback-porch = < 0x14 >;
  3620. vfront-porch = < 0x05 >;
  3621. hsync-len = < 0x28 >;
  3622. vsync-len = < 0x05 >;
  3623. hsync-active = < 0x01 >;
  3624. vsync-active = < 0x01 >;
  3625. de-active = < 0x00 >;
  3626. pixelclk-active = < 0x00 >;
  3627. swap-rb = < 0x00 >;
  3628. swap-rg = < 0x00 >;
  3629. swap-gb = < 0x00 >;
  3630. };
  3631.  
  3632. timing1 {
  3633. screen-type = < 0x01 >;
  3634. out-face = < 0x00 >;
  3635. color-mode = < 0x02 >;
  3636. clock-frequency = < 0x8d9ee20 >;
  3637. hactive = < 0x780 >;
  3638. vactive = < 0x438 >;
  3639. hback-porch = < 0x94 >;
  3640. hfront-porch = < 0x58 >;
  3641. vback-porch = < 0x24 >;
  3642. vfront-porch = < 0x04 >;
  3643. hsync-len = < 0x2c >;
  3644. vsync-len = < 0x05 >;
  3645. hsync-active = < 0x01 >;
  3646. vsync-active = < 0x01 >;
  3647. de-active = < 0x00 >;
  3648. pixelclk-active = < 0x00 >;
  3649. swap-rb = < 0x00 >;
  3650. swap-rg = < 0x00 >;
  3651. swap-gb = < 0x00 >;
  3652. linux,phandle = < 0xb3 >;
  3653. phandle = < 0xb3 >;
  3654. };
  3655.  
  3656. timing2 {
  3657. screen-type = < 0x01 >;
  3658. out-face = < 0x00 >;
  3659. color-mode = < 0x02 >;
  3660. clock-frequency = < 0x11b3dc40 >;
  3661. hactive = < 0xf00 >;
  3662. vactive = < 0x870 >;
  3663. hback-porch = < 0x128 >;
  3664. hfront-porch = < 0xb0 >;
  3665. vback-porch = < 0x48 >;
  3666. vfront-porch = < 0x08 >;
  3667. hsync-len = < 0x58 >;
  3668. vsync-len = < 0x0a >;
  3669. hsync-active = < 0x01 >;
  3670. vsync-active = < 0x01 >;
  3671. de-active = < 0x00 >;
  3672. pixelclk-active = < 0x00 >;
  3673. swap-rb = < 0x00 >;
  3674. swap-rg = < 0x00 >;
  3675. swap-gb = < 0x00 >;
  3676. };
  3677.  
  3678. timing3 {
  3679. screen-type = < 0x05 >;
  3680. out-face = < 0x00 >;
  3681. color-mode = < 0x02 >;
  3682. clock-frequency = < 0x19bfcc0 >;
  3683. hactive = < 0x2d0 >;
  3684. vactive = < 0x1e0 >;
  3685. hback-porch = < 0x2b >;
  3686. hfront-porch = < 0x21 >;
  3687. vback-porch = < 0x13 >;
  3688. vfront-porch = < 0x00 >;
  3689. hsync-len = < 0x3e >;
  3690. vsync-len = < 0x03 >;
  3691. hsync-active = < 0x01 >;
  3692. vsync-active = < 0x01 >;
  3693. de-active = < 0x00 >;
  3694. pixelclk-active = < 0x01 >;
  3695. swap-rb = < 0x00 >;
  3696. swap-rg = < 0x00 >;
  3697. swap-gb = < 0x00 >;
  3698. interlaced;
  3699. };
  3700.  
  3701. timing4 {
  3702. screen-type = < 0x05 >;
  3703. out-face = < 0x00 >;
  3704. color-mode = < 0x02 >;
  3705. clock-frequency = < 0x19bfcc0 >;
  3706. hactive = < 0x2d0 >;
  3707. vactive = < 0x240 >;
  3708. hback-porch = < 0x30 >;
  3709. hfront-porch = < 0x21 >;
  3710. vback-porch = < 0x13 >;
  3711. vfront-porch = < 0x02 >;
  3712. hsync-len = < 0x3f >;
  3713. vsync-len = < 0x03 >;
  3714. hsync-active = < 0x01 >;
  3715. vsync-active = < 0x01 >;
  3716. de-active = < 0x00 >;
  3717. pixelclk-active = < 0x01 >;
  3718. swap-rb = < 0x00 >;
  3719. swap-rg = < 0x00 >;
  3720. swap-gb = < 0x00 >;
  3721. interlaced;
  3722. };
  3723.  
  3724. timing5 {
  3725. screen-type = < 0x01 >;
  3726. out-face = < 0x00 >;
  3727. color-mode = < 0x02 >;
  3728. clock-frequency = < 0x3dfd240 >;
  3729. hactive = < 0x400 >;
  3730. vactive = < 0x300 >;
  3731. hback-porch = < 0xa0 >;
  3732. hfront-porch = < 0x18 >;
  3733. vback-porch = < 0x1d >;
  3734. vfront-porch = < 0x03 >;
  3735. hsync-len = < 0x88 >;
  3736. vsync-len = < 0x06 >;
  3737. hsync-active = < 0x01 >;
  3738. vsync-active = < 0x01 >;
  3739. de-active = < 0x00 >;
  3740. pixelclk-active = < 0x00 >;
  3741. swap-rb = < 0x00 >;
  3742. swap-rg = < 0x00 >;
  3743. swap-gb = < 0x00 >;
  3744. };
  3745. };
  3746.  
  3747. wireless-wlan {
  3748. compatible = "wlan-platdata";
  3749. wifi_chip_type = "rtl8189fs";
  3750. sdio_vref = < 0x708 >;
  3751. WIFI,poweren_gpio = < 0x74 0x1c 0x00 >;
  3752. WIFI,host_wake_irq = < 0x7b 0x1a 0x00 >;
  3753. status = "disabled";
  3754. };
  3755.  
  3756. wireless-bluetooth {
  3757. compatible = "bluetooth-platdata";
  3758. uart_rts_gpios = < 0xb4 0x06 0x01 >;
  3759. pinctrl-names = "default\0rts_gpio";
  3760. pinctrl-0 = < 0xb5 >;
  3761. pinctrl-1 = < 0xb6 >;
  3762. BT,power_gpio = < 0x7b 0x1d 0x00 >;
  3763. BT,wake_gpio = < 0xb4 0x1b 0x00 >;
  3764. BT,wake_host_irq = < 0xb4 0x1a 0x00 >;
  3765. status = "disabled";
  3766. };
  3767.  
  3768. rk_4g {
  3769. compatible = "rockchip,rk_4g";
  3770. pinctrl-names = "default";
  3771. pinctrl-0 = < 0xb7 >;
  3772. mcu_scl_gpio = < 0xb4 0x14 0x00 >;
  3773. mcu_sda_gpio = < 0x8c 0x00 0x00 >;
  3774. status = "okay";
  3775. };
  3776.  
  3777. regulators {
  3778. compatible = "simple-bus";
  3779. #address-cells = < 0x01 >;
  3780. #size-cells = < 0x00 >;
  3781.  
  3782. regulator@0 {
  3783. compatible = "regulator-fixed";
  3784. regulator-name = "vccio_1v8";
  3785. regulator-min-microvolt = < 0x1b7740 >;
  3786. regulator-max-microvolt = < 0x1b7740 >;
  3787. regulator-always-on;
  3788. linux,phandle = < 0x5d >;
  3789. phandle = < 0x5d >;
  3790. };
  3791.  
  3792. regulator@1 {
  3793. compatible = "regulator-fixed";
  3794. regulator-name = "vccio_3v3";
  3795. regulator-min-microvolt = < 0x325aa0 >;
  3796. regulator-max-microvolt = < 0x325aa0 >;
  3797. regulator-always-on;
  3798. linux,phandle = < 0x5c >;
  3799. phandle = < 0x5c >;
  3800. };
  3801. };
  3802.  
  3803. pwm-regulator1 {
  3804. compatible = "rockchip_pwm_regulator";
  3805. pwms = < 0xb8 0x00 0x1388 >;
  3806. rockchip,pwm_id = < 0x01 >;
  3807. rockchip,pwm_voltage_map = < 0xe7ef0 0xee098 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 0x1437c8 0x149970 0x14fb18 0x155cc0 >;
  3808. rockchip,pwm_voltage = < 0x10c8e0 >;
  3809. rockchip,pwm_min_voltage = < 0xe7ef0 >;
  3810. rockchip,pwm_max_voltage = < 0x155cc0 >;
  3811. rockchip,pwm_suspend_voltage = < 0xe7ef0 >;
  3812. rockchip,pwm_coefficient = < 0x1c2 >;
  3813. status = "okay";
  3814.  
  3815. regulators {
  3816. #address-cells = < 0x01 >;
  3817. #size-cells = < 0x00 >;
  3818.  
  3819. regulator@0 {
  3820. regulator-compatible = "pwm_dcdc1";
  3821. regulator-name = "vdd_arm";
  3822. regulator-min-microvolt = < 0xe7ef0 >;
  3823. regulator-max-microvolt = < 0x155cc0 >;
  3824. regulator-always-on;
  3825. regulator-boot-on;
  3826. };
  3827. };
  3828. };
  3829.  
  3830. pwm-regulator2 {
  3831. compatible = "rockchip_pwm_regulator";
  3832. pwms = < 0xb9 0x00 0x1388 >;
  3833. rockchip,pwm_id = < 0x02 >;
  3834. rockchip,pwm_voltage_map = < 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 >;
  3835. rockchip,pwm_voltage = < 0x124f80 >;
  3836. rockchip,pwm_min_voltage = < 0xf4240 >;
  3837. rockchip,pwm_max_voltage = < 0x13d620 >;
  3838. rockchip,pwm_suspend_voltage = < 0x1312d0 >;
  3839. rockchip,pwm_coefficient = < 0x12c >;
  3840. status = "okay";
  3841.  
  3842. regulators {
  3843. #address-cells = < 0x01 >;
  3844. #size-cells = < 0x00 >;
  3845.  
  3846. regulator@1 {
  3847. regulator-compatible = "pwm_dcdc2";
  3848. regulator-name = "vdd_logic";
  3849. regulator-min-microvolt = < 0xf4240 >;
  3850. regulator-max-microvolt = < 0x13d620 >;
  3851. regulator-always-on;
  3852. regulator-boot-on;
  3853. };
  3854. };
  3855. };
  3856.  
  3857. usb_control {
  3858. compatible = "rockchip,rk322x-usb-control";
  3859. rockchip,remote_wakeup;
  3860. rockchip,usb_irq_wakeup;
  3861. otg_drv_gpio = < 0xb4 0x16 0x01 >;
  3862. };
  3863.  
  3864. rockchip_audio {
  3865. compatible = "rockchip,rk322x-audio";
  3866.  
  3867. dais {
  3868.  
  3869. dai0 {
  3870. audio-codec = < 0xba >;
  3871. audio-controller = < 0xbb >;
  3872. format = "i2s";
  3873. };
  3874. };
  3875. };
  3876.  
  3877. rockchip_spdif_card {
  3878. compatible = "rockchip-spdif-card";
  3879.  
  3880. dais {
  3881.  
  3882. dai0 {
  3883. audio-codec = < 0xbc >;
  3884. audio-controller = < 0xbd >;
  3885. };
  3886. };
  3887. };
  3888.  
  3889. rockchip_hdmi_i2s {
  3890. compatible = "rockchip-hdmi-i2s";
  3891.  
  3892. dais {
  3893.  
  3894. dai0 {
  3895. audio-codec = < 0xbe >;
  3896. audio-controller = < 0xbf >;
  3897. format = "i2s";
  3898. };
  3899. };
  3900. };
  3901.  
  3902. rockchip_nau8540 {
  3903. status = "disabled";
  3904. compatible = "rockchip,nau8540-audio";
  3905.  
  3906. dais {
  3907.  
  3908. dai0 {
  3909. audio-codec = < 0xc0 >;
  3910. audio-controller = < 0xbb >;
  3911. format = "i2s";
  3912. };
  3913. };
  3914. };
  3915.  
  3916. power-led {
  3917. compatible = "gpio-leds";
  3918. gpios = < 0x8c 0x07 0x01 >;
  3919.  
  3920. green {
  3921. gpios = < 0xb4 0x15 0x00 >;
  3922. default-state = "on";
  3923. };
  3924. };
  3925.  
  3926. hc_key {
  3927. compatible = "rockchip,hckey";
  3928. status = "okay";
  3929.  
  3930. gpio1-key {
  3931. gpios = < 0xb4 0x17 0x01 >;
  3932. linux,code = < 0x01 >;
  3933. label = "gpio1";
  3934. };
  3935.  
  3936. gpio2-key {
  3937. gpios = < 0x8c 0x01 0x01 >;
  3938. linux,code = < 0x02 >;
  3939. label = "gpio2";
  3940. };
  3941.  
  3942. gpio3-key {
  3943. gpios = < 0x74 0x02 0x01 >;
  3944. linux,code = < 0x03 >;
  3945. label = "gpio3";
  3946. };
  3947.  
  3948. gpio4-key {
  3949. gpios = < 0xb4 0x19 0x01 >;
  3950. linux,code = < 0x04 >;
  3951. label = "gpio4";
  3952. };
  3953.  
  3954. gpio5-key {
  3955. gpios = < 0x8c 0x0a 0x01 >;
  3956. linux,code = < 0x05 >;
  3957. label = "gpio5";
  3958. };
  3959. };
  3960. };
  3961.  
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