module xyz(
	input T,clk,aclr,
	output reg Q);

	always @(posedge clk, negedge aclr)
		if (!aclr) 		Q <= 1'b0;
		else if (T) 	Q <= ~Q;
		else		Q <=  Q;
endmodule


module xyzx(
	input clk,aclr,enable,
	output [7:0] q);

	wire [7:1] c;

	assign c[1] = q[0] & enable;
	assign c[2] = q[1] & c[1];
	assign c[3] = q[2] & c[2];
	assign c[4] = q[3] & c[3];
	assign c[5] = q[4] & c[4];
	assign c[6] = q[5] & c[5];
	assign c[7] = q[6] & c[6];


	xyz ex0(enable,clk,aclr,q[0]);
	xyz ex1(c[1],clk,aclr,q[1]);
	xyz ex2(c[2],clk,aclr,q[2]);
	xyz ex3(c[3],clk,aclr,q[3]);
	xyz ex4(c[4],clk,aclr,q[4]);
	xyz ex5(c[5],clk,aclr,q[5]);
	xyz ex6(c[6],clk,aclr,q[6]);
	xyz ex7(c[7],clk,aclr,q[7]);
endmodule

module adder_1(
	input [9:0] SW,
	input [3:0] KEY,
	output [0:6] HEX0, HEX1);
	integer sum, cout, mod16, multiple16, _sum;
	wire [7:0] h;

	xyzx ex0(KEY[0],SW[0],SW[1],h);

	always@(SW[8:0] or h[7:0]) begin
		if(SW[8:0] > h[7:0]) begin
			sum = SW[9:0] - h[7:0];
		end
		else begin
			sum = h[7:0] - SW[9:0];
		end
		mod16 = sum % 16;
		multiple16 = sum / 16;
		end

		dis ex2(mod16,HEX0);
		dis ex3(multiple16,HEX1);
endmodule

module dis(
    input [7:0] a,
    output reg [0:6] H);
    always @(*)
        case (a)
            0: H = 7'b0000001;
            1: H = 7'b1001111;
            2: H = 7'b0010010;
            3: H = 7'b0000110;
            4: H = 7'b1001100;
            5: H = 7'b0100100;
            6: H = 7'b0100000;
            7: H = 7'b0001111;
            8: H = 7'b0000000;
            9: H = 7'b0000100;
            10: H = 7'b0001000;
            11: H = 7'b1100000;
            12: H = 7'b0110001;
            13: H = 7'b1000010;
            14: H = 7'b0110000;
            15: H = 7'b0111000;
            default: H = 7'b1111111;
            endcase
endmodule