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May 12th, 2018
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  1. $ cat memory_controller.v
  2. module memory_controller(clk,
  3.              devices_mem_en,
  4.              device_1_mem_addr,
  5.              device_2_mem_addr,
  6.              device_3_mem_addr,
  7.              device_1_mem_di,
  8.              device_2_mem_di,
  9.              device_3_mem_di,
  10.              devices_mem_we,
  11.              devices_do_ack,
  12.              mem_do);
  13.  
  14. input   clk;
  15. input   [2:0] devices_mem_en;
  16. input   [7:0] device_1_mem_addr;
  17. input   [7:0] device_2_mem_addr;
  18. input   [7:0] device_3_mem_addr;
  19. input   [7:0] device_1_mem_di;
  20. input   [7:0] device_2_mem_di;
  21. input   [7:0] device_3_mem_di;
  22. input   [2:0] devices_mem_we;
  23. output  [2:0] devices_do_ack;
  24. output  [7:0] mem_do;
  25.  
  26. parameter DEVICE_1 = 3'd0;
  27. parameter DEVICE_2 = 3'd1;
  28. parameter DEVICE_3 = 3'd2;
  29. parameter NO_ONE = 3'b111;
  30.  
  31. reg mem_enable = 0;
  32. reg [7:0] mem_addr = 7'd0;
  33. reg [7:0] mem_di = 7'd0;
  34. reg [2:0] current_slave = NO_ONE;
  35. reg mem_we = 0;
  36. reg [2:0] serving_slave = 2'd0;
  37. reg [2:0] devices_do_ack = 3'd0;
  38.  
  39. always @(posedge clk)
  40. begin
  41.     if (current_slave == NO_ONE)
  42.         mem_enable <= 0;
  43.     else
  44.         mem_enable <= devices_mem_en[0] | devices_mem_en[1] | devices_mem_en[2];
  45. end
  46.  
  47. always @(posedge clk)
  48. begin
  49.     case (current_slave)
  50.        
  51.     DEVICE_1:
  52.     begin
  53.         mem_addr <= device_1_mem_addr;
  54.         mem_di <= device_1_mem_di;
  55.         mem_we <= devices_mem_we[0];
  56.     end
  57.  
  58.     DEVICE_2:
  59.     begin
  60.         mem_addr <= device_2_mem_addr;
  61.         mem_di <= device_2_mem_di;
  62.         mem_we <= devices_mem_we[1];
  63.     end
  64.    
  65.     DEVICE_3:
  66.     begin
  67.         mem_addr <= device_3_mem_addr;
  68.         mem_di <= device_3_mem_di;
  69.         mem_we <= devices_mem_we[2];
  70.     end
  71.  
  72.     NO_ONE:
  73.     begin
  74.         mem_addr <= 7'd0;
  75.         mem_di <= 7'd0;
  76.         mem_we <= 0;
  77.     end
  78.  
  79.     endcase
  80. end
  81.  
  82. always @(posedge clk)
  83. begin
  84.  
  85.     case(current_slave)
  86.  
  87.     NO_ONE:
  88.     begin
  89.         devices_do_ack = 3'b000;
  90.         if (devices_mem_en[0])
  91.             current_slave <= DEVICE_1;
  92.         else if (devices_mem_en[1])
  93.             current_slave <= DEVICE_2;
  94.         else if (devices_mem_en[2])
  95.             current_slave <= DEVICE_3;
  96.         else
  97.             current_slave <= NO_ONE;
  98.     end
  99.  
  100.     DEVICE_1:
  101.     begin
  102.         devices_do_ack = 3'b001;
  103.         if (devices_mem_en[1])
  104.             current_slave <= DEVICE_2;
  105.         else if (devices_mem_en[2])
  106.             current_slave <= DEVICE_3;
  107.     end
  108.  
  109.     DEVICE_2:
  110.     begin
  111.         devices_do_ack = 3'b010;
  112.         if (devices_mem_en[2])
  113.             current_slave <= DEVICE_3;
  114.         else if (devices_mem_en[0])
  115.             current_slave <= DEVICE_1;
  116.     end
  117.    
  118.     DEVICE_3:
  119.     begin
  120.         devices_do_ack = 3'b100;
  121.         if (devices_mem_en[0])
  122.             current_slave <= DEVICE_1;
  123.         else if (devices_mem_en[1])
  124.             current_slave <= DEVICE_2;
  125.     end
  126.  
  127.     endcase
  128. end
  129.  
  130. ram mem(clk, mem_enable, mem_addr, mem_di, mem_do, mem_we);
  131.  
  132. endmodule
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