`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.04.2022 22:36:20
// Design Name:
// Module Name: hypotenuse_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module hypotenuse_test();
    reg[7:0] a, b;
    reg clk, rst;
    reg start;
    wire[8:0] rez;
    wire busy;
    wire[16:0] sum;

    hypotenuse my_hypotenuse(clk, rst, start, a, b, rez, busy, sum);

    initial begin
        a = 15; b = 30; // 33
        test();

        a = 3; b = 4; // 5
        test();

        a = 6; b = 8; // 10
        test();

        a = 10; b = 100; // 100
        test();

        a = 0; b = 0; // 0
        test();

        a = 125; b = 125; // 176
        test();

        a = 255; b = 255; // 360
        test();

        clk = 0; #10
        $stop;
    end

    task test;
        begin
            start = 0;

            clk = 0; #10

            clk = 1; rst = 1; #10

            clk = 0; rst = 0; #10
            start = 1;

            clk = 1; #10
            start = 0;
            clk = 0; #10 clk = 1; #10;

            while(busy)
            begin
                clk = 0;
                #10
                clk = 1;
                #10;
            end
        end
    endtask
endmodule