module decoder_4_7_bit (
    input [3:0] X,
    output reg [6:0] H
);

    always @(*)
        case (X[3:0])
            4'b0000:
            begin
                H = 7'b1000000;
            end
            4'b0001:
            begin
                H = 7'b1111001;
            end
            4'b0010:
            begin
                H = 7'b0100100;
            end
            4'b0011:
            begin
                H = 7'b0110000;
            end
            4'b0100:
            begin
                H = 7'b0011001;
            end
            4'b0101:
            begin
                H = 7'b0010010;
            end
            4'b0110:
            begin
                H = 7'b0000010;
            end
            4'b0111:
            begin
                H = 7'b1111000;
            end
            4'b1000:
            begin
                H = 7'b0000000;
            end
            4'b1001:
            begin
                H = 7'b0010000;
            end
        default:
            begin
                H = 7'b1111111;
            end
        endcase

endmodule

module decoder_4_7_bit_hex (
    input [3:0] X,
    output reg [6:0] H
);

    always @(*)
        case (X[3:0])
            4'b0000:
            begin
                H = 7'b1000000;
            end
            4'b0001:
            begin
                H = 7'b1111001;
            end
            4'b0010:
            begin
                H = 7'b0100100;
            end
            4'b0011:
            begin
                H = 7'b0110000;
            end
            4'b0100:
            begin
                H = 7'b0011001;
            end
            4'b0101:
            begin
                H = 7'b0010010;
            end
            4'b0110:
            begin
                H = 7'b0000010;
            end
            4'b0111:
            begin
                H = 7'b1111000;
            end
            4'b1000:
            begin
                H = 7'b0000000;
            end
            4'b1001:
            begin
                H = 7'b0010000;
            end
            4'b1010:
            begin
                H = 7'b0001000;
            end
            4'b1011:
            begin
                H = 7'b0000011;
            end
            4'b1100:
            begin
                H = 7'b1000110;
            end
            4'b1101:
            begin
                H = 7'b0100001;
            end
            4'b1110:
            begin
                H = 7'b0000110;
            end
            4'b1111:
            begin
                H = 7'b0001110;
            end
        default:
            begin
                H = 7'b1111111;
            end
        endcase

endmodule

module decoder_hex_10 (
    input [3:0]A1, A0,
    output reg [1:0] ERR,
    output [6:0] H1, H0
);

    always @(*)
        begin
            if (A1 > 4'b1001)
                ERR[1] = 1;
            else
                ERR[1] = 0;

            if (A0 > 4'b1001)
                ERR[0] = 1;
            else
                ERR[0] = 0;
        end

    decoder_4_7_bit ex0 (A1[3:0], H1[6:0]);
    decoder_4_7_bit ex1 (A0[3:0], H0[6:0]);

endmodule

//module Zadanie2 (
//  input [7:0] SW,
//  output [9:0] LEDR,
//  output [6:0] HEX0, HEX1
//);
//
// decoder_hex_10 ex (SW[7:4], SW[3:0], LEDR[9:8], HEX1[6:0], HEX0[6:0]);
//
// assign LEDR[7:0] = SW[7:0];
//
//endmodule


module decoder_hex_16 (
    input [3:0]A1, A0,
    output [6:0] H1, H0
);


    decoder_4_7_bit_hex ex0 (A1[3:0], H1[6:0]);
    decoder_4_7_bit_hex ex1 (A0[3:0], H0[6:0]);

endmodule

//module Zadanie2 (
//  input [7:0] SW,
//  output [9:0] LEDR,
//  output [6:0] HEX0, HEX1
//);
//
// decoder_hex_16 ex (SW[7:4], SW[3:0], HEX1[6:0], HEX0[6:0]);
//
// assign LEDR[7:0] = SW[7:0];
//
//endmodule