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Astralix

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Astralix
Jun 29th, 2013
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  1. 300MHz
  2. Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=8 Size=2048MB
  3. OUT
  4. BUILD=====5
  5. F:32 1061 2 0 40
  6. GetRemapTbl flag = 0
  7. OK! 49729
  8. unsigned!
  9. SecureBootEn = 0 0
  10. Boot ver: 2013-05-18#1.20
  11. start_linux=====61316
  12. 715275 Starting kernel...@0x60408000
  13.  
  14. [ 0.000000] Initializing cgroup subsys cpu
  15. [ 0.000000] Linux version 3.0.36omegamoon+ (uprinz@BigBox) (gcc version 4.4.3 (GCC) ) #1 SMP PREEMPT Sun Jun 30 00:29:00 CEST 2013
  16. [ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
  17. [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
  18. [ 0.000000] Machine: RK30board
  19. [ 0.000000] memory reserve: Memory(base:0x91800000 size:80M) reserved for <ion>
  20. [ 0.000000] memory reserve: Memory(base:0x90d00000 size:11M) reserved for <fb0 buf>
  21. [ 0.000000] memory reserve: Total reserved 91M
  22. [ 0.000000] Memory policy: ECC disabled, Data cache writeback
  23. [ 0.000000] bootconsole [earlycon0] enabled
  24. [ 0.000000] CPU SRAM: copied sram code from c0bca000 to fef00100 - fef022d0
  25. [ 0.000000] CPU SRAM: copied sram data from c0bcc1d0 to fef022d0 - fef02a4c
  26. [ 0.000000] sram_log: 4q ?& : 4q ?) !?, # 0q *! ! 3q @ 3q
  27. [ 0.000000] CLKDATA_MSG: pll_flag = 0x00
  28. [ 0.000000] clk_enable xin24m with 24000000
  29. [ 0.000000] clk_enable ddr_pll with 300000000
  30. [ 0.000000] clk_enable ddr with 300000000
  31. [ 0.000000] clk_enable xin24m with 24000000
  32. [ 0.000000] clk_enable arm_pll with 600000000
  33. [ 0.000000] clk_enable cpu_div with 18750000
  34. [ 0.000000] clk_enable xin24m with 24000000
  35. [ 0.000000] clk_enable general_pll with 891000000
  36. [ 0.000000] clk_enable cpu_gpll_path with 891000000
  37. [ 0.000000] clk_enable arm_pll with 600000000
  38. [ 0.000000] clk_enable core with 600000000
  39. [ 0.000000] clk_enable l2c with 600000000
  40. [ 0.000000] clk_enable core with 600000000
  41. [ 0.000000] clk_enable core_dbg with 600000000
  42. [ 0.000000] clk_enable core with 600000000
  43. [ 0.000000] clk_enable core_periph with 150000000
  44. [ 0.000000] clk_enable core with 600000000
  45. [ 0.000000] clk_enable aclk_core with 300000000
  46. [ 0.000000] clk_enable cpu_div with 18750000
  47. [ 0.000000] clk_enable aclk_cpu with 18750000
  48. [ 0.000000] clk_enable pclk_cpu with 9375000
  49. [ 0.000000] clk_enable atclk_cpu with 9375000
  50. [ 0.000000] clk_enable aclk_cpu with 18750000
  51. [ 0.000000] clk_enable hclk_cpu with 18750000
  52. [ 0.000000] clk_enable ahb2apb with 9375000
  53. [ 0.000000] clk_enable xin24m with 24000000
  54. [ 0.000000] clk_enable uart2 with 24000000
  55. [ 0.000000] clk_enable general_pll with 891000000
  56. [ 0.000000] clk_enable aclk_periph with 27843750
  57. [ 0.000000] clk_enable pclk_periph with 13921875
  58. [ 0.000000] clk_enable pclk_uart2 with 13921875
  59. [ 0.000000] clk_enable aclk_cpu with 18750000
  60. [ 0.000000] clk_enable dma1 with 18750000
  61. [ 0.000000] clk_enable aclk_cpu with 18750000
  62. [ 0.000000] clk_enable intmem with 18750000
  63. [ 0.000000] clk_enable aclk_cpu with 18750000
  64. [ 0.000000] clk_enable aclk_strc_sys with 18750000
  65. [ 0.000000] clk_enable hclk_cpu with 18750000
  66. [ 0.000000] clk_enable rom with 18750000
  67. [ 0.000000] clk_enable hclk_cpu with 18750000
  68. [ 0.000000] clk_enable hclk_cpubus with 18750000
  69. [ 0.000000] clk_enable hclk_cpu with 18750000
  70. [ 0.000000] clk_enable hclk_ahb2apb with 18750000
  71. [ 0.000000] clk_enable hclk_cpu with 18750000
  72. [ 0.000000] clk_enable hclk_vio_bus with 18750000
  73. [ 0.000000] clk_enable hclk_cpu with 18750000
  74. [ 0.000000] clk_enable hclk_imem0 with 18750000
  75. [ 0.000000] clk_enable hclk_cpu with 18750000
  76. [ 0.000000] clk_enable hclk_imem1 with 18750000
  77. [ 0.000000] clk_enable pclk_cpu with 9375000
  78. [ 0.000000] clk_enable tzpc with 9375000
  79. [ 0.000000] clk_enable pclk_cpu with 9375000
  80. [ 0.000000] clk_enable pclk_ddrupctl with 9375000
  81. [ 0.000000] clk_enable pclk_cpu with 9375000
  82. [ 0.000000] clk_enable pclk_ddrpubl with 9375000
  83. [ 0.000000] clk_enable pclk_cpu with 9375000
  84. [ 0.000000] clk_enable dbg with 9375000
  85. [ 0.000000] clk_enable pclk_cpu with 9375000
  86. [ 0.000000] clk_enable grf with 9375000
  87. [ 0.000000] clk_enable pclk_cpu with 9375000
  88. [ 0.000000] clk_enable pmu with 9375000
  89. [ 0.000000] clk_enable aclk_periph with 27843750
  90. [ 0.000000] clk_enable dma2 with 27843750
  91. [ 0.000000] clk_enable aclk_periph with 27843750
  92. [ 0.000000] clk_enable aclk_smc with 27843750
  93. [ 0.000000] clk_enable aclk_periph with 27843750
  94. [ 0.000000] clk_enable aclk_peri_niu with 27843750
  95. [ 0.000000] clk_enable aclk_periph with 27843750
  96. [ 0.000000] clk_enable aclk_cpu_peri with 27843750
  97. [ 0.000000] clk_enable aclk_periph with 27843750
  98. [ 0.000000] clk_enable aclk_peri_axi_matrix with 27843750
  99. [ 0.000000] clk_enable aclk_periph with 27843750
  100. [ 0.000000] clk_enable hclk_periph with 27843750
  101. [ 0.000000] clk_enable hclk_peri_axi_matrix with 27843750
  102. [ 0.000000] clk_enable hclk_periph with 27843750
  103. [ 0.000000] clk_enable hclk_peri_ahb_arbi with 27843750
  104. [ 0.000000] clk_enable hclk_periph with 27843750
  105. [ 0.000000] clk_enable hclk_emem_peri with 27843750
  106. [ 0.000000] clk_enable hclk_periph with 27843750
  107. [ 0.000000] clk_enable nandc with 27843750
  108. [ 0.000000] clk_enable hclk_periph with 27843750
  109. [ 0.000000] clk_enable hclk_usb_peri with 27843750
  110. [ 0.000000] clk_enable pclk_periph with 13921875
  111. [ 0.000000] clk_enable pclk_peri_axi_matrix with 13921875
  112. [ 0.000000] clk_enable general_pll with 594000000
  113. [ 0.000000] L310 cache controller enabled
  114. [ 0.000000] l2x0: 16 ways, CACHE_ID 0x4100c0c8, AUX_CTRL 0x76050001, Cache size: 524288 B
  115. [ 0.000000] DDR DEBUG: version 1.00 20130427
  116. [ 0.000000] DDR DEBUG: DDR3 Device
  117. [ 0.000000] DDR DEBUG: Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Total Capability=2048MB
  118. [ 0.000000] DDR DEBUG: init success!!! freq=396MHz
  119. [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
  120. [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
  121. [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
  122. [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
  123. [ 0.000000] DDR DEBUG: ZERR=0, ZDONE=0, ZPD=0x0, ZPU=0x0, OPD=0x0, OPU=0x0
  124. [ 0.000000] DDR DEBUG: DRV Pull-Up=0xb, DRV Pull-Dwn=0xb
  125. [ 0.000000] DDR DEBUG: ODT Pull-Up=0x2, ODT Pull-Dwn=0x2
  126. [ 0.000000] clk_enable general_pll with 594000000
  127. [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
  128. [ 0.000000] clk_enable aclk_vio1 with 297000000
  129. [ 0.000000] clk_enable aclk_rga with 297000000
  130. [ 0.000000] clk_enable general_pll with 594000000
  131. [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
  132. [ 0.000000] clk_enable aclk_vio1 with 297000000
  133. [ 0.000000] clk_enable aclk_lcdc1 with 297000000
  134. [ 0.000000] clk_enable general_pll with 594000000
  135. [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
  136. [ 0.000000] clk_enable aclk_vio1 with 297000000
  137. [ 0.000000] clk_enable general_pll with 594000000
  138. [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
  139. [ 0.000000] clk_enable aclk_vio0 with 297000000
  140. [ 0.000000] clk_enable aclk_ipp with 297000000
  141. [ 0.000000] clk_enable general_pll with 594000000
  142. [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
  143. [ 0.000000] clk_enable aclk_vio0 with 297000000
  144. [ 0.000000] clk_enable aclk_cif0 with 297000000
  145. [ 0.000000] clk_enable general_pll with 594000000
  146. [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
  147. [ 0.000000] clk_enable aclk_vio0 with 297000000
  148. [ 0.000000] clk_enable aclk_lcdc0 with 297000000
  149. [ 0.000000] clk_enable general_pll with 594000000
  150. [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
  151. [ 0.000000] clk_enable aclk_vio0 with 297000000
  152. [ 0.000000] clk_enable pclk_periph with 74250000
  153. [ 0.000000] clk_enable pclk_saradc with 74250000
  154. [ 0.000000] clk_enable pclk_periph with 74250000
  155. [ 0.000000] clk_enable gpio3 with 74250000
  156. [ 0.000000] clk_enable pclk_periph with 74250000
  157. [ 0.000000] clk_enable i2c4 with 74250000
  158. [ 0.000000] clk_enable pclk_periph with 74250000
  159. [ 0.000000] clk_enable i2c3 with 74250000
  160. [ 0.000000] clk_enable pclk_periph with 74250000
  161. [ 0.000000] clk_enable i2c2 with 74250000
  162. [ 0.000000] clk_enable pclk_periph with 74250000
  163. [ 0.000000] clk_enable pclk_uart3 with 74250000
  164. [ 0.000000] clk_enable pclk_periph with 74250000
  165. [ 0.000000] clk_enable pclk_spi1 with 74250000
  166. [ 0.000000] clk_enable pclk_periph with 74250000
  167. [ 0.000000] clk_enable pclk_spi0 with 74250000
  168. [ 0.000000] clk_enable pclk_periph with 74250000
  169. [ 0.000000] clk_enable wdt with 74250000
  170. [ 0.000000] clk_enable pclk_periph with 74250000
  171. [ 0.000000] clk_enable pwm23 with 74250000
  172. [ 0.000000] clk_enable hclk_periph with 148500000
  173. [ 0.000000] clk_enable hclk_emmc with 148500000
  174. [ 0.000000] clk_enable hclk_periph with 148500000
  175. [ 0.000000] clk_enable hclk_sdio with 148500000
  176. [ 0.000000] clk_enable hclk_periph with 148500000
  177. [ 0.000000] clk_enable hclk_sdmmc with 148500000
  178. [ 0.000000] clk_enable hclk_periph with 148500000
  179. [ 0.000000] clk_enable hclk_pidfilter with 148500000
  180. [ 0.000000] clk_enable hclk_periph with 148500000
  181. [ 0.000000] clk_enable hclk_hsadc with 148500000
  182. [ 0.000000] clk_enable hclk_periph with 148500000
  183. [ 0.000000] clk_enable hclk_hsic with 148500000
  184. [ 0.000000] clk_enable hclk_usb_peri with 148500000
  185. [ 0.000000] clk_enable hclk_otg1 with 148500000
  186. [ 0.000000] clk_enable hclk_usb_peri with 148500000
  187. [ 0.000000] clk_enable hclk_otg0 with 148500000
  188. [ 0.000000] clk_enable hclk_periph with 148500000
  189. [ 0.000000] clk_enable hclk_mac with 148500000
  190. [ 0.000000] clk_enable aclk_periph with 148500000
  191. [ 0.000000] clk_enable aclk_gps with 148500000
  192. [ 0.000000] clk_enable ahb2apb with 74250000
  193. [ 0.000000] clk_enable pclk_uart1 with 74250000
  194. [ 0.000000] clk_enable ahb2apb with 74250000
  195. [ 0.000000] clk_enable pclk_uart0 with 74250000
  196. [ 0.000000] clk_enable pclk_cpu with 74250000
  197. [ 0.000000] clk_enable efuse with 74250000
  198. [ 0.000000] clk_enable pclk_cpu with 74250000
  199. [ 0.000000] clk_enable gpio2 with 74250000
  200. [ 0.000000] clk_enable pclk_cpu with 74250000
  201. [ 0.000000] clk_enable gpio1 with 74250000
  202. [ 0.000000] clk_enable pclk_cpu with 74250000
  203. [ 0.000000] clk_enable gpio0 with 74250000
  204. [ 0.000000] clk_enable pclk_cpu with 74250000
  205. [ 0.000000] clk_enable i2c1 with 74250000
  206. [ 0.000000] clk_enable pclk_cpu with 74250000
  207. [ 0.000000] clk_enable i2c0 with 74250000
  208. [ 0.000000] clk_enable pclk_cpu with 74250000
  209. [ 0.000000] clk_enable pclk_timer2 with 74250000
  210. [ 0.000000] clk_enable pclk_cpu with 74250000
  211. [ 0.000000] clk_enable pclk_timer0 with 74250000
  212. [ 0.000000] clk_enable pclk_cpu with 74250000
  213. [ 0.000000] clk_enable pwm01 with 74250000
  214. [ 0.000000] clk_enable hclk_cpu with 148500000
  215. [ 0.000000] clk_enable hclk_rga with 148500000
  216. [ 0.000000] clk_enable hclk_cpu with 148500000
  217. [ 0.000000] clk_enable hclk_ipp with 148500000
  218. [ 0.000000] clk_enable hclk_cpu with 148500000
  219. [ 0.000000] clk_enable hclk_cif0 with 148500000
  220. [ 0.000000] clk_enable hclk_cpu with 148500000
  221. [ 0.000000] clk_enable hclk_lcdc1 with 148500000
  222. [ 0.000000] clk_enable hclk_cpu with 148500000
  223. [ 0.000000] clk_enable hclk_lcdc0 with 148500000
  224. [ 0.000000] clk_enable hclk_cpu with 148500000
  225. [ 0.000000] clk_enable hclk_spdif with 148500000
  226. [ 0.000000] clk_enable hclk_cpu with 148500000
  227. [ 0.000000] clk_enable hclk_i2s0_2ch with 148500000
  228. [ 0.000000] clk_enable xin24m with 24000000
  229. [ 0.000000] clk_enable timer6 with 24000000
  230. [ 0.000000] clk_enable xin24m with 24000000
  231. [ 0.000000] clk_enable timer5 with 24000000
  232. [ 0.000000] clk_enable xin24m with 24000000
  233. [ 0.000000] clk_enable timer4 with 24000000
  234. [ 0.000000] clk_enable xin24m with 24000000
  235. [ 0.000000] clk_enable timer3 with 24000000
  236. [ 0.000000] clk_enable xin24m with 24000000
  237. [ 0.000000] clk_enable timer2 with 24000000
  238. [ 0.000000] clk_enable xin24m with 24000000
  239. [ 0.000000] clk_enable timer1 with 24000000
  240. [ 0.000000] clk_enable xin24m with 24000000
  241. [ 0.000000] clk_enable timer0 with 24000000
  242. [ 0.000000] clk_enable general_pll with 594000000
  243. [ 0.000000] clk_enable uart_pll with 594000000
  244. [ 0.000000] clk_enable uart3_div with 49500000
  245. [ 0.000000] clk_enable uart3_frac_div with 2475000
  246. [ 0.000000] clk_enable general_pll with 594000000
  247. [ 0.000000] clk_enable uart_pll with 594000000
  248. [ 0.000000] clk_enable uart3_div with 49500000
  249. [ 0.000000] clk_enable general_pll with 594000000
  250. [ 0.000000] clk_enable uart_pll with 594000000
  251. [ 0.000000] clk_enable uart2_div with 49500000
  252. [ 0.000000] clk_enable uart2_frac_div with 2475000
  253. [ 0.000000] clk_enable general_pll with 594000000
  254. [ 0.000000] clk_enable uart_pll with 594000000
  255. [ 0.000000] clk_enable uart2_div with 49500000
  256. [ 0.000000] clk_enable general_pll with 594000000
  257. [ 0.000000] clk_enable uart_pll with 594000000
  258. [ 0.000000] clk_enable uart1_div with 49500000
  259. [ 0.000000] clk_enable uart1_frac_div with 2475000
  260. [ 0.000000] clk_enable general_pll with 594000000
  261. [ 0.000000] clk_enable uart_pll with 594000000
  262. [ 0.000000] clk_enable uart1_div with 49500000
  263. [ 0.000000] clk_enable general_pll with 594000000
  264. [ 0.000000] clk_enable uart_pll with 594000000
  265. [ 0.000000] clk_enable uart0_div with 49500000
  266. [ 0.000000] clk_enable uart0_frac_div with 2475000
  267. [ 0.000000] clk_enable general_pll with 594000000
  268. [ 0.000000] clk_enable uart_pll with 594000000
  269. [ 0.000000] clk_enable uart0_div with 49500000
  270. [ 0.000000] clk_enable hclk_periph with 148500000
  271. [ 0.000000] clk_enable emmc with 37125000
  272. [ 0.000000] clk_enable hclk_periph with 148500000
  273. [ 0.000000] clk_enable sdio with 24750000
  274. [ 0.000000] clk_enable hclk_periph with 148500000
  275. [ 0.000000] clk_enable sdmmc with 24750000
  276. [ 0.000000] clk_enable pclk_periph with 74250000
  277. [ 0.000000] clk_enable spi1 with 74250000
  278. [ 0.000000] clk_enable pclk_periph with 74250000
  279. [ 0.000000] clk_enable spi0 with 74250000
  280. [ 0.000000] clk_enable hclk_periph with 148500000
  281. [ 0.000000] clk_enable smc with 148500000
  282. [ 0.000000] clk_enable xin24m with 24000000
  283. [ 0.000000] clk_enable saradc with 93750
  284. [ 0.000000] clk_enable general_pll with 594000000
  285. [ 0.000000] clk_enable hsadc_pll_div with 2320312
  286. [ 0.000000] clk_enable hsadc_frac_div with 116015
  287. [ 0.000000] clk_enable general_pll with 594000000
  288. [ 0.000000] clk_enable hsadc_pll_div with 2320312
  289. [ 0.000000] clk_enable ddr_pll with 396000000
  290. [ 0.000000] clk_enable mac_pll_div with 33000000
  291. [ 0.000000] clk_enable mac_ref with 33000000
  292. [ 0.000000] clk_enable mii_tx with 33000000
  293. [ 0.000000] clk_enable ddr_pll with 396000000
  294. [ 0.000000] clk_enable mac_pll_div with 33000000
  295. [ 0.000000] clk_enable xin24m with 24000000
  296. [ 0.000000] clk_enable otgphy1 with 24000000
  297. [ 0.000000] clk_enable xin24m with 24000000
  298. [ 0.000000] clk_enable otgphy0 with 24000000
  299. [ 0.000000] clk_enable general_pll with 594000000
  300. [ 0.000000] clk_enable i2s_pll with 594000000
  301. [ 0.000000] clk_enable spdif_div with 9281250
  302. [ 0.000000] clk_enable spdif_frac_div with 464062
  303. [ 0.000000] clk_enable general_pll with 594000000
  304. [ 0.000000] clk_enable i2s_pll with 594000000
  305. [ 0.000000] clk_enable spdif_div with 9281250
  306. [ 0.000000] clk_enable general_pll with 594000000
  307. [ 0.000000] clk_enable i2s_pll with 594000000
  308. [ 0.000000] clk_enable i2s0_div with 9281250
  309. [ 0.000000] clk_enable i2s0_frac_div with 0
  310. [ 0.000000] clk_enable general_pll with 594000000
  311. [ 0.000000] clk_enable i2s_pll with 594000000
  312. [ 0.000000] clk_enable i2s0_div with 9281250
  313. [ 0.000000] clk_enable pclkin_cif0 with 0
  314. [ 0.000000] clk_enable general_pll with 594000000
  315. [ 0.000000] clk_enable cif_out_pll with 594000000
  316. [ 0.000000] clk_enable cif0_out_div with 18562500
  317. [ 0.000000] clk_enable general_pll with 594000000
  318. [ 0.000000] clk_enable dclk_lcdc1 with 2320312
  319. [ 0.000000] clk_enable general_pll with 594000000
  320. [ 0.000000] clk_enable dclk_lcdc0 with 2320312
  321. [ 0.000000] clk_enable general_pll with 594000000
  322. [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
  323. [ 0.000000] clk_enable general_pll with 594000000
  324. [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
  325. [ 0.000000] clk_enable general_pll with 594000000
  326. [ 0.000000] clk_enable aclk_vdpu with 297000000
  327. [ 0.000000] clk_enable hclk_vdpu with 74250000
  328. [ 0.000000] clk_enable general_pll with 594000000
  329. [ 0.000000] clk_enable aclk_vdpu with 297000000
  330. [ 0.000000] clk_enable general_pll with 594000000
  331. [ 0.000000] clk_enable aclk_vepu with 297000000
  332. [ 0.000000] clk_enable hclk_vepu with 74250000
  333. [ 0.000000] clk_enable general_pll with 594000000
  334. [ 0.000000] clk_enable aclk_vepu with 297000000
  335. [ 0.000000] clk_enable xin24m with 24000000
  336. [ 0.000000] clk_enable codec_pll with 798000000
  337. [ 0.000000] clk_enable aclk_gpu with 199500000
  338. [ 0.000000] clk_enable general_pll with 594000000
  339. [ 0.000000] clk_enable ddr_gpll_path with 594000000
  340. [ 0.000000] clk_enable xin24m with 24000000
  341. [ 0.000000] clk_enable codec_pll with 798000000
  342. [ 0.000000] PERCPU: Embedded 7 pages/cpu @c313f000 s7008 r8192 d13472 u32768
  343. [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 496896
  344. [ 0.000000] Kernel command line: console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init initrd=0x62000000,0x00130000 mtdparts=rk29xxnand:0x00002000@0x00002000(misc),0x00006000@0x00004000(kernel),0x00008000@0x0000A000(boot),0x00010000@0x00012000(recovery),0x00020000@0x00022000(backup),0x00040000@0x00042000(cache),0x00400000@0x00082000(userdata),0x00002000@0x00482000(kpanic),0x00100000@0x00484000(system),-@0x00584000(user) bootver=2013-05-18#1.20 firmware_ver=4.1.1
  345. [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
  346. [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
  347. [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
  348. [ 0.000000] Memory: 781MB 1176MB = 1957MB total
  349. [ 0.000000] Memory: 1966496k/1966496k available, 130656k reserved, 1204224K highmem
  350. [ 0.000000] Virtual kernel memory layout:
  351. [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
  352. [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
  353. [ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
  354. [ 0.000000] vmalloc : 0xf7000000 - 0xfe800000 ( 120 MB)
  355. [ 0.000000] lowmem : 0xc0000000 - 0xf6800000 ( 872 MB)
  356. [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
  357. [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
  358. [ 0.000000] .init : 0xc0408000 - 0xc0512000 (1064 kB)
  359. [ 0.000000] .text : 0xc0512000 - 0xc0b605f4 (6458 kB)
  360. [ 0.000000] .data : 0xc0b62000 - 0xc0bc98a8 ( 415 kB)
  361. [ 0.000000] .bss : 0xc0bcd024 - 0xc1672a50 (10903 kB)
  362. [ 0.000000] SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
  363. [ 0.000000] Preemptible hierarchical RCU implementation.
  364. [ 0.000000] NR_IRQS:352
  365. [ 0.000000] clk_enable pclk_cpu with 74250000
  366. [ 0.000000] clk_enable gpio0 with 74250000
  367. [ 0.000000] clk_enable pclk_cpu with 74250000
  368. [ 0.000000] clk_enable gpio1 with 74250000
  369. [ 0.000000] clk_enable pclk_cpu with 74250000
  370. [ 0.000000] clk_enable gpio2 with 74250000
  371. [ 0.000000] clk_enable pclk_periph with 74250000
  372. [ 0.000000] clk_enable gpio3 with 74250000
  373. [ 0.000000] rk30_gpio_init: 128 gpio irqs in 4 banks
  374. [ 0.000000] clk_enable pclk_cpu with 74250000
  375. [ 0.000000] clk_enable pclk_timer0 with 74250000
  376. [ 0.000000] clk_enable xin24m with 24000000
  377. [ 0.000000] clk_enable timer0 with 24000000
  378. [ 0.000000] clk_enable pclk_timer0 with 74250000
  379. [ 0.000000] clk_enable xin24m with 24000000
  380. [ 0.000000] clk_enable timer1 with 24000000
  381. [ 0.000000] clk_enable pclk_timer0 with 74250000
  382. [ 0.000000] clk_enable xin24m with 24000000
  383. [ 0.000000] clk_enable timer4 with 24000000
  384. [ 0.000000] clk_enable pclk_timer0 with 74250000
  385. [ 0.000000] clk_enable xin24m with 24000000
  386. [ 0.000000] clk_enable timer5 with 24000000
  387. [ 0.000000] clk_enable pclk_timer0 with 74250000
  388. [ 0.000000] clk_enable xin24m with 24000000
  389. [ 0.000000] clk_enable timer6 with 24000000
  390. [ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
  391. [ 0.000000] rk_timer: version 1.2
  392. [ 0.000000] Console: colour dummy device 80x30
  393. [ 0.008622] Calibrating delay loop (skipped) preset value.. 1631.46 BogoMIPS (lpj=8157341)
  394. [ 0.017645] pid_max: default: 32768 minimum: 301
  395. [ 0.022923] Mount-cache hash table entries: 512
  396. [ 0.028475] Initializing cgroup subsys debug
  397. [ 0.033187] Initializing cgroup subsys cpuacct
  398. [ 0.038142] Initializing cgroup subsys freezer
  399. [ 0.043059] CPU: Testing write buffer coherency: ok
  400. [ 0.129082] CPU1: Booted secondary processor
  401. [ 0.169078] CPU2: Booted secondary processor
  402. [ 0.209079] CPU3: Booted secondary processor
  403. [ 0.209118] Brought up 4 CPUs
  404. [ 0.226592] SMP: Total of 4 processors activated (6525.87 BogoMIPS).
  405. [ 0.233900] devtmpfs: initialized
  406. [ 0.243747] NET: Registered protocol family 16
  407. [ 0.248720] last_log: 0xf0900000 map to 0xf7004000 and copy to 0xc0bd1180 (version 2.1)
  408. [ 0.271121] warning:lcdc0 not add to system!
  409. [ 0.275900] lcdc1 is used as primary display device controller!
  410. [ 0.282673] rk29sdk_wifi_bt_gpio_control_init: request wifi power gpio failed
  411. <hit enter to activate fiq debugger>
  412. 0.291939] console [ttyFIQ0] enabled, bootconsole disabled
  413. [ 0.291939] console [ttyFIQ0] enabled, bootconsole disabled
  414. [ 0.300988] Registered FIQ tty driver f083dcc0
  415. [ 0.314348] bio: create slab <bio-0> at 0
  416. [ 0.318786] SCSI subsystem initialized
  417. [ 0.319015] usbcore: registered new interface driver usbfs
  418. [ 0.319138] usbcore: registered new interface driver hub
  419. [ 0.333360] usbcore: registered new device driver usb
  420. [ 0.333504] clk_enable pclk_cpu with 74250000
  421. [ 0.333536] clk_enable i2c0 with 74250000
  422. [ 0.333663] rk30_i2c rk30_i2c.0: i2c-0: RK30 I2C adapter
  423. [ 0.333721] clk_enable pclk_cpu with 74250000
  424. [ 0.333752] clk_enable i2c1 with 74250000
  425. [ 0.333960] rk30_i2c rk30_i2c.1: i2c-1: RK30 I2C adapter
  426. [ 0.334020] clk_enable pclk_periph with 74250000
  427. [ 0.334051] clk_enable i2c2 with 74250000
  428. [ 0.334226] rk30_i2c rk30_i2c.2: i2c-2: RK30 I2C adapter
  429. [ 0.334286] clk_enable pclk_periph with 74250000
  430. [ 0.334317] clk_enable i2c3 with 74250000
  431. [ 0.334421] rk30_i2c rk30_i2c.3: i2c-3: RK30 I2C adapter
  432. [ 0.334480] clk_enable pclk_periph with 74250000
  433. [ 0.334511] clk_enable i2c4 with 74250000
  434. [ 0.334614] rk30_i2c rk30_i2c.4: i2c-4: RK30 I2C adapter
  435. [ 0.407299] clk_enable pclk_periph with 74250000
  436. [ 0.407335] clk_enable pclk_saradc with 74250000
  437. [ 0.407386] clk_enable xin24m with 24000000
  438. [ 0.407415] clk_enable saradc with 1000000
  439. [ 0.407455] rk30-adc rk30-adc: rk30 adc: driver initialized
  440. [ 0.407742] Advanced Linux Sound Architecture Driver Version 1.0.24.
  441. [ 0.408185] Bluetooth: Core ver 2.16
  442. [ 0.408253] NET: Registered protocol family 31
  443. [ 0.408285] Bluetooth: HCI device and connection manager initialized
  444. [ 0.408329] Bluetooth: HCI socket layer initialized
  445. [ 0.408363] Bluetooth: L2CAP socket layer initialized
  446. [ 0.408410] Bluetooth: SCO socket layer initialized
  447. [ 0.409481] rk fb probe ok!
  448. [ 0.409577] clk_enable i2c1 with 74250000
  449. [ 0.409852] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 2...
  450. [ 0.409909] clk_enable i2c1 with 74250000
  451. [ 0.410177] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 1...
  452. [ 0.410232] clk_enable i2c1 with 74250000
  453. [ 0.410498] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 0...
  454. [ 0.410553] The device is not act8846
  455. [ 0.410612] i2c-core: driver [act8846] using legacy suspend method
  456. [ 0.410652] i2c-core: driver [act8846] using legacy resume method
  457. [ 0.410712] Switching to clocksource rk_timer
  458. [ 0.417539] lcdc1:reg_phy_base = 0x1010e000,reg_vir_base:0xf70a0000
  459. [ 0.417609] fb0:win0
  460. [ 0.417614] fb1:win1
  461. [ 0.417619] fb2:win2
  462. [ 0.417692] clk_enable hclk_cpu with 148500000
  463. [ 0.417722] clk_enable hclk_lcdc1 with 148500000
  464. [ 0.417754] clk_enable general_pll with 594000000
  465. [ 0.417785] clk_enable dclk_lcdc1 with 2320312
  466. [ 0.417816] clk_enable general_pll with 594000000
  467. [ 0.417847] clk_enable aclk_lcdc1_pre with 297000000
  468. [ 0.417879] clk_enable aclk_vio1 with 297000000
  469. [ 0.417909] clk_enable aclk_lcdc1 with 297000000
  470. [ 0.417945] clk_enable pd_vio with 0
  471. [ 0.417969] clk_enable pd_lcdc1 with 0
  472. [ 0.417995] rk3188 lcdc1 clk enable...
  473. [ 0.418038] rk3188 lcdc1 clk disable...
  474. [ 0.418073] lcdc1: dclk:74250000>>fps:60
  475. [ 0.418104] rk30-lcdc rk30-lcdc.1: rk3188_load_screen for lcdc1 ok!
  476. [ 0.418606] Switched to NOHz mode on CPU #0
  477. [ 0.419113] Switched to NOHz mode on CPU #3
  478. [ 0.419129] Switched to NOHz mode on CPU #1
  479. [ 0.419144] Switched to NOHz mode on CPU #2
  480. [ 0.440346] fb0:phy:90d00000>>vir:f8000000>>len:0xb00000
  481. [ 0.440689] rk_fb_register>>>>>fb0
  482. [ 0.440897] rk_fb_register>>>>>fb1
  483. [ 0.440927] clk_enable hclk_cpu with 148500000
  484. [ 0.440957] clk_enable hclk_lcdc1 with 148500000
  485. [ 0.440988] clk_enable general_pll with 594000000
  486. [ 0.441019] clk_enable dclk_lcdc1 with 74250000
  487. [ 0.441050] clk_enable general_pll with 594000000
  488. [ 0.441081] clk_enable aclk_lcdc1_pre with 297000000
  489. [ 0.441113] clk_enable aclk_vio1 with 297000000
  490. [ 0.441142] clk_enable aclk_lcdc1 with 297000000
  491. [ 0.441184] clk_enable pd_vio with 0
  492. [ 0.441208] clk_enable pd_lcdc1 with 0
  493. [ 0.441234] rk3188 lcdc1 clk enable...
  494. [ 0.441260] lcdc1 wakeup from standby!
  495. [ 0.441287] lcdc1 win0 open,atv layer:1
  496. [ 0.441322] lcdc1>>win0_set_par>>format:2>>>xact:1280>>yact:720>>xsize:1280>>ysize:720>>xvir:1280>>yvir:720>>xpos:260>>ypos:25>>
  497. [ 0.460462] lcdc1>>win0_display:y_addr:0x90d00000>>uv_addr:0x0
  498. [ 0.460507] rk3188 lcdc1 probe ok!
  499. [ 0.460648] HDMI: hdmi_register() - video source 1 display 0
  500. [ 0.460932] HDMI: hdmi_submit_work event 0100 delay 0
  501. [ 0.461067] HDMI:
  502. [ 0.461073] hdmi_work_queue() - evt= 1 0
  503. [ 0.461111] HDMI: hdmi_work_queue() - exit
  504. [ 0.461120]
  505. [ 0.461268] clk_enable i2c2 with 74250000
  506. [ 0.461754] clk_enable i2c2 with 74250000
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