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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 10:53:44 07/28/2022
- // Design Name:
- // Module Name: FullAdder
- // Project Name: Ripple Adder
- // Target Devices: Nexys 4
- // Description:
- // Flow Level, ecuaciones logicas
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module FullAdder(
- input A,
- input B,
- input C,
- output SUM,
- output COUT
- );
- assign SUM=A ^ B ^ C;
- assign COUT=(A&B) | (C&(A ^ B));
- endmodule
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