library ieee;
use ieee.std_logic_1164.all;

entity TestTimesTen is
port(
SW:in std_logic_vector(5 downto 0);
HEX3,HEX2,HEX1,HEX0: out std_logic_vector(6 downto 0)
);
end entity TestTimesTen;

Architecture behaviour of TestTimesTen is
signal set1,set2,set3,set4,set5: std_logic_vector(9 downto 0);
signal X:std_logic_vector(5 downto 0);
signal TenX: std_logic_vector(9 downto 0);
component SegDecoder
port(D:in std_logic_vector(3 downto 0);
	Y:out std_logic_vector(6 downto 0));
	end component;
component TimesTen
port(
X:in std_logic_vector(5 downto 0);
TenX:out std_logic_vector(9 downto 0));
end component;
begin
	X(5 downto 0) <= SW(5 downto 0);
TT0:TimesTen port map(X=> X(5 downto 0), TenX=> set2(9 downto 0));
SD1:SegDecoder port map(D => set2(9 downto 6), Y=> HEX3(6 downto 0));
TT1:TimesTen port map(X=> set2(5 downto 0), TenX=> set3(9 downto 0));
SD2:SegDecoder port map(D => set3(9 downto 6), Y=> HEX2(6 downto 0));
TT2:TimesTen port map(X=> set3(5 downto 0), TenX=> set4(9 downto 0));
SD3:SegDecoder port map(D => set4(9 downto 6), Y=> HEX1(6 downto 0));
TT3:TimesTen port map(X=> set4(5 downto 0), TenX=> set5(9 downto 0));
SD4:SegDecoder port map(D => set5(9 downto 6), Y=> HEX0(6 downto 0));

end architecture behaviour;