imximage.cfg

#define __ASSEMBLY__
#include <config.h>

IMAGE_VERSION	2
BOOT_FROM	sd

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

DATA 4 0x30340004 0x4F400005

//=============================================================================
// DDR Controller Registers
//=============================================================================
// Memory type:	LPDDR3
// Manufacturer:	Kingston
// Device Part Number:	"08EMCP04-NL3DT227-A01U"
// Clock Freq.: 	533MHz
// Density per CS in Gb: 	4
// Chip Selects used:	1
// Number of Banks:	8
// Row address:    	14
// Column address: 	10
// Data bus width:	32
// ROW-BANK interleave:	ENABLED
//=============================================================================

DATA 4 0x30391000 0x00000002		// deassert presetn
DATA 4 0x307A0000 0x01040008		// DDRC_MSTR
DATA 4 0x307A0064 0x00200038		// DDRC_RFSHTMG
DATA 4 0x307a0490 0x00000001		// DDRC_PCTRL_0
//DATA 4 0x307A00D4 0x00010000		# DDRC_INIT1 (if using LPDDR3/LPDDR2, this line is automatically commented out)
DATA 4 0x307A00D0 0x00350001		// DDRC_INIT0
DATA 4 0x307A00D8 0x00001105		// DDRC_INIT2  (if using DDR3 this line is automatically commented out)
DATA 4 0x307A00DC 0x00C3000A		// DDRC_INIT3
DATA 4 0x307A00E0 0x00020000		// DDRC_INIT4
DATA 4 0x307A00E4 0x00110006		// DDRC_INIT5
DATA 4 0x307A00F4 0x0000033F		// DDRC_RANKCTL
DATA 4 0x307A0100 0x0A0E110B		// DDRC_DRAMTMG0
DATA 4 0x307A0104 0x00020211		// DDRC_DRAMTMG1
DATA 4 0x307A0108 0x03060708		// DDRC_DRAMTMG2
DATA 4 0x307A010C 0x00A0500C		// DDRC_DRAMTMG3
DATA 4 0x307A0110 0x05020307		// DDRC_DRAMTMG4
DATA 4 0x307A0114 0x02020404		// DDRC_DRAMTMG5
DATA 4 0x307A0118 0x02020003		// DDRC_DRAMTMG6
DATA 4 0x307A011C 0x00000202		// DDRC_DRAMTMG7
DATA 4 0x307A0120 0x00000202		// DDRC_DRAMTMG8
DATA 4 0x307A0180 0x20600018		// DDRC_ZQCTL0
DATA 4 0x307A0184 0x00E00100		// DDRC_ZQCTL1
DATA 4 0x307A0190 0x02098205		// DDRC_DFITMG0
DATA 4 0x307A0194 0x00060303		// DDRC_DFITMG1
DATA 4 0x307A01A0 0x80400003		// DDRC_DFIUPD0
DATA 4 0x307A01A4 0x00100020		// DDRC_DFIUPD1
DATA 4 0x307A01A8 0x80100004		// DDRC_DFIUPD2
DATA 4 0x307A0200 0x0000001F		// DDRC_ADDRMAP0
DATA 4 0x307A0204 0x00080808		// DDRC_ADDRMAP1
DATA 4 0x307A020C 0x00000000		// DDRC_ADDRMAP3
DATA 4 0x307A0210 0x00000F0F		// DDRC_ADDRMAP4
DATA 4 0x307A0214 0x07070707		// DDRC_ADDRMAP5
DATA 4 0x307A0218 0x0F0F0707		// DDRC_ADDRMAP6
DATA 4 0x307A0240 0x06000600		// DDRC_ODTCFG
DATA 4 0x307A0244 0x00000000		// DDRC_ODTMAP

//=============================================================================
// PHY Control Registers
//=============================================================================

DATA 4 0x30391000 0x00000000		// deassert presetn
DATA 4 0x30790000 0x17421E40		// DDR_PHY_PHY_CON0
DATA 4 0x30790004 0x10210100		// DDR_PHY_PHY_CON1
DATA 4 0x30790008 0x00010000		// DDR_PHY_PHY_CON2 (if using DDR3 this line is automatically commented out)
DATA 4 0x30790010 0x0007080C		// DDR_PHY_PHY_CON4
DATA 4 0x307900B0 0x1010007E		// DDR_PHY_MDLL_CON0
DATA 4 0x3079001C 0x01010000		// DDR_PHY_PHY_RODT_CON0 (if using DDR3 this line is automatically commented out)
DATA 4 0x3079009C 0x00000D6E		// DDR_PHY_DRVDS_CON0

//DATA 4 0x30790078 0x00000001		# DDR_PHY_WR_LVL_CON3 - Optional write leveling resync enable, uncomment to invoke
//DATA 4 0x3079006C 0x00000000		# DDR_PHY_WR_LVL_CON0 - Optional write leveling values for each byte lane, uncomment to invoke
//DATA 4 0x30790078 0x00000000		# DDR_PHY_WR_LVL_CON3 - Optional write leveling resync disable, uncomment to invoke

DATA 4 0x30790030 0x06060606		// DDR_PHY_OFFSET_WR_CON0
DATA 4 0x30790020 0x06060606		// DDR_PHY_OFFSET_RD_CON0
DATA 4 0x30790050 0x01000008		// DDR_PHY_OFFSETD_CON0
DATA 4 0x30790050 0x00000008		// DDR_PHY_OFFSETD_CON0
DATA 4 0x30790018 0x0000000F		// DDR_PHY_LP_CON0
DATA 4 0x307900C0 0x0E487304		// DDR_PHY_ZQ_CON0 - Start Manual ZQ
DATA 4 0x307900C0 0x0E4C7304
DATA 4 0x307900C0 0x0E4C7306
// 	<= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
DATA 4 0x307900C0 0x0E487304		// DDR_PHY_ZQ_CON0 - End Manual ZQ


//=============================================================================
// Final Initialization start sequence
//=============================================================================

DATA 4 0x30384130 0x00000000		//Disable Clock
DATA 4 0x30340020 0x00000178		// IOMUX_GRP_GRP8 - Start input to PHY
DATA 4 0x30384130 0x00000002		//Enable Clock

DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002

CHECK_BITS_SET 4 0x307a0004 0x1