Bai Thi

module Bai1(input CLOCK_50, input SW, output [0:6] HEX0);
reg [24:0] dem;
reg [8:0] a;

always @(posedge CLOCK_50)
dem=dem+1'b1;

always @(posedge dem[24])
if (SW==1'b1) a=a+1'b1;
else if (a==1'b0)
begin
a=8'd100;
a=a-1'b1;
end
else a=a-1'b1;

assign HEX0= (a%10==8'd0)? 8'd1:
(a%10==8'd1)? 8'd79:
(a%10==8'd2)? 8'd18:
(a%10==8'd3)? 8'd6:
(a%10==8'd4)? 8'd76:
(a%10==8'd5)? 8'd36:
(a%10==8'd6)? 8'd32:
(a%10==8'd7)? 8'd15:
(a%10==8'd8)? 8'd0: 8'd4;


endmodule

//===============================

module HA (a,b,s,co);
input a,b;
output s,co;
assign s=a^b;
assign co=a&b;
endmodule

module FA (a,b,ci,s,co);
input a,b,ci;
output s,co;
assign s=(a^b)^ci;
assign co=(a&b)|(a&ci)|(b&ci);
endmodule

module Bai2(a,b,s,hex0,hex1);
input [3:0] a,b;
output [4:0] s;
output [0:6] hex0;
output [0:6] hex1;
wire c1,c2,c3;

HA u0 (.a(a[0]),.b(b[0]),.s(s[0]),.co(c1));
FA u1 (.a(a[1]),.b(b[1]),.ci(c1),.s(s[1]),.co(c2));
FA u2 (.a(a[2]),.b(b[2]),.ci(c2),.s(s[2]),.co(c3));
FA u3 (.a(a[3]),.b(b[3]),.ci(c3),.s(s[3]),.co(s[4]));

wire [3:0] dv,ch;
assign dv=s%10;
assign ch=s/10;

assign hex0= (dv==0)? 1:
(dv==1)? 79:
(dv==2)? 18:
(dv==3)? 6:
(dv==4)? 76:
(dv==5)? 36:
(dv==6)? 32:
(dv==7)? 15:
(dv==8)? 0: 4;

assign hex1= (ch==0)? 1:
(ch==1)? 79:
(ch==2)? 18:
(ch==3)? 6:
(ch==4)? 76:
(ch==5)? 36:
(ch==6)? 32:
(ch==7)? 15:
(ch==8)? 0: 4;

endmodule

//========================================

module Bai3 (CLOCK_50, LEDG);
input CLOCK_50;
output reg [7:0] LEDG;
reg [24:0] dem;
reg [1:0] flag;

always @(posedge CLOCK_50)
dem=dem+1'b1;

always @(posedge dem[23])
if (LEDG==8'd0) LEDG=8'd2;
else if (flag==2'b0)
begin
LEDG={LEDG[6:0],LEDG[7]};   // DICH TRAI
if (LEDG[7]==2'b1) flag=2'b1;
end
else
begin
LEDG={LEDG[0],LEDG[7:1]};    //DICH PHAI
if (LEDG[0]==2'b1) flag=2'b0;
end

endmodule

//==========================================
module Bai5 (input CLOCK_50, output reg [7:0] LEDG);

reg [24:0] dem;

always @(posedge CLOCK_50)
dem=dem+1'b1;

always @(posedge dem[24])
if (LEDG==8'd0) LEDG=8'd129;
else LEDG={LEDG[4],LEDG[7:5],LEDG[2:0],LEDG[3]};

endmodule


//=========================================

module Bai6(input CLOCK_50, input [1:0] SW, output reg [0:6] HEX0, HEX1, HEX2, HEX3, HEX4);
reg [24:0] dem;
reg [1:0] flag;
reg [6:0] speed;

always @(posedge CLOCK_50)
dem=dem+1'b1;

always @(posedge dem[speed])
begin
if (SW==2'b0)
begin
speed = 6'd24;
if (flag==2'b0)
begin
HEX4=8'd72;
HEX3=8'd48;
HEX2=8'd113;
HEX1=8'd113;
HEX0=8'd1;
flag=2'b1;
end

else
begin
HEX4=8'd255;
HEX3=8'd255;
HEX2=8'd255;
HEX1=8'd255;
HEX0=8'd255;
flag=2'b0;
end
end

else if (SW==2'b1)
begin
speed = 6'd23;
if (flag==2'b0)
begin
HEX4=8'd72;
HEX3=8'd48;
HEX2=8'd113;
HEX1=8'd113;
HEX0=8'd1;
flag=2'b1;
end

else
begin
HEX4=8'd255;
HEX3=8'd255;
HEX2=8'd255;
HEX1=8'd255;
HEX0=8'd255;
flag=2'b0;
end
end

else if (SW==2'b10)
begin
speed = 6'd22;
if (flag==2'b0)
begin
HEX4=8'd72;
HEX3=8'd48;
HEX2=8'd113;
HEX1=8'd113;
HEX0=8'd1;
flag=2'b1;
end

else
begin
HEX4=8'd255;
HEX3=8'd255;
HEX2=8'd255;
HEX1=8'd255;
HEX0=8'd255;
flag=2'b0;
end
end

else if (SW==2'b11)
begin
speed = 6'd21;
if (flag==2'b0)
begin
HEX4=8'd72;
HEX3=8'd48;
HEX2=8'd113;
HEX1=8'd113;
HEX0=8'd1;
flag=2'b1;
end

else
begin
HEX4=8'd255;
HEX3=8'd255;
HEX2=8'd255;
HEX1=8'd255;
HEX0=8'd255;
flag=2'b0;
end
end
end


endmodule

//============================================


module Bai7(input [8:0] sw, output [0:6] hex0, hex1, hex2,tr,ch,dv);

assign tr=sw/8'd100;
assign ch=(sw/8'd10)%8'd10;
assign dv = sw%8'd10;

assign hex0= (dv==8'd0)? 8'd1:
(dv==8'd1)? 8'd79:
(dv==8'd2)? 8'd18:
(dv==8'd3)? 8'd6:
(dv==8'd4)? 8'd76:
(dv==8'd5)? 8'd36:
(dv==8'd6)? 8'd32:
(dv==8'd7)? 8'd15:
(dv==8'd8)? 8'd0:
(dv==8'd9)? 8'd4:8'd255;

assign hex1= (ch==8'd0)? 8'd1:
(ch==8'd1)? 8'd79:
(ch==8'd2)? 8'd18:
(ch==8'd3)? 8'd6:
(ch==8'd4)? 8'd76:
(ch==8'd5)? 8'd36:
(ch==8'd6)? 8'd32:
(ch==8'd7)? 8'd15:
(ch==8'd8)? 8'd0:
(ch==8'd9)? 8'd4:8'd255;

assign hex2= (tr==8'd0)? 8'd1:
(tr==8'd1)? 8'd79:
(tr==8'd2)? 8'd18:
(tr==8'd3)? 8'd6:
(tr==8'd4)? 8'd76:
(tr==8'd5)? 8'd36:
(tr==8'd6)? 8'd32:
(tr==8'd7)? 8'd15:
(tr==8'd8)? 8'd0:
(tr==8'd9)? 8'd4:8'd255;

endmodule



//=================================

module Bai8(input CLOCK_50, output reg [0:6] hex0, hex1, hex2,c);

reg [24:0] dem;

always @(posedge CLOCK_50)
dem=dem+1;

always @(posedge dem[24])
if (c==0)
begin
hex2=79;
hex1=255;
hex0=72;
c=1;
end
else if (c==1)
begin
hex2=72;
hex1=79;
hex0=255;
c=2;
end
else
begin
hex2=255;
hex1=72;
hex0=79;
c=0;
end

endmodule



//=================================

module Bai9 (input CLOCK_50, output reg [7:0] LEDR);

reg [24:0] dem;
reg [1:0] flag;

always @(posedge CLOCK_50)
dem=dem+1'b1;

always @(posedge dem[22])
if (flag==2'b0)
begin
LEDR={~LEDR[0],LEDR[7:1]};
if (LEDR==8'd255) flag=2'b1;
end
else
begin
LEDR={LEDR[6:0],~LEDR[7]};
if (LEDR==8'd0) flag=2'b0;
end

endmodule
//==================================


module Bai10(sw, hex0, hex1, hex2,a,tr,ch,dv);
input [3:0] sw;
output [0:6] hex0,hex1,hex2,tr,ch,dv;
output [0:7] a;

assign a=sw;
assign tr=(a*a)/7'd100;
assign ch=((a*a)/7'd10)%7'd10;
assign dv = (a*a)%7'd10;

assign hex0= (dv==8'd0)? 8'd1:
(dv==8'd1)? 8'd79:
(dv==8'd2)? 8'd18:
(dv==8'd3)? 8'd6:
(dv==8'd4)? 8'd76:
(dv==8'd5)? 8'd36:
(dv==8'd6)? 8'd32:
(dv==8'd7)? 8'd15:
(dv==8'd8)? 8'd0:
(dv==8'd9)? 8'd4:8'd255;

assign hex1= (ch==8'd0)? 8'd1:
(ch==8'd1)? 8'd79:
(ch==8'd2)? 8'd18:
(ch==8'd3)? 8'd6:
(ch==8'd4)? 8'd76:
(ch==8'd5)? 8'd36:
(ch==8'd6)? 8'd32:
(ch==8'd7)? 8'd15:
(ch==8'd8)? 8'd0:
(ch==8'd9)? 8'd4:8'd255;

assign hex2= (tr==8'd0)? 8'd1:
(tr==8'd1)? 8'd79:
(tr==8'd2)? 8'd18:
(tr==8'd3)? 8'd6:
(tr==8'd4)? 8'd76:
(tr==8'd5)? 8'd36:
(tr==8'd6)? 8'd32:
(tr==8'd7)? 8'd15:
(tr==8'd8)? 8'd0:
(tr==8'd9)? 8'd4:8'd255;

endmodule