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- import os
- from myhdl import Cosimulation
- from myhdl import always_comb, toVHDL, Signal, intbv
- cmd = 'vsim -c -quiet -pli myhdl_vpi.so -do cosim.do dut_bin2gray'
- def bin2gray_rtl(B, G):
- """ Gray encoder.
- B -- input intbv signal, binary encoded
- G -- output intbv signal, gray encoded
- """
- @always_comb
- def logic():
- ext_b = intbv(0)[len(B)+1:0]
- ext_b[:] = B
- for i in range(len(B)):
- G.next[i] = ext_b[i+1] ^ ext_b[i]
- return logic
- def bin2gray(B, G):
- toVHDL.name = "bin2gray"
- toVHDL(bin2gray_rtl, B, G)
- os.system('vlib work')
- os.system('vcom -quiet -work work pck_myhdl_090.vhd')
- os.system('vcom -quiet -work work bin2gray.vhd')
- os.system('vlog -quiet -work work +define+width=%s dut_bin2gray.v' % (len(B)))
- print("All sources compiled")
- return Cosimulation(cmd, B=B, G=G)
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