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  1. module EXE2WB(clk, WB, mem_out, alu_result, mux1_w_reg, mux1_w_reg_O, alu_O, mem_out_O, mux3, regwrt
  2.     );
  3. input clk;
  4. input [1:0] WB;
  5. input [7:0] mem_out;
  6. input [7:0] alu_result;
  7. input [3:0] mux1_w_reg;
  8.  
  9. output reg [3:0] mux1_w_reg_O;
  10. output reg [7:0] alu_O, mem_out_O;
  11. output reg mux3;
  12. output reg regwrt;
  13.  
  14. always @(negedge clk)begin
  15. mux1_w_reg_O <=  mux1_w_reg;
  16. alu_O <= alu_result;
  17. mem_out_O <= mem_out;
  18. mux3 <= WB[1];
  19. regwrt <= WB[0];
  20. end
  21.  
  22.  
  23.  
  24. endmodule
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