first_draft

module testik(input clock,input A,input B, output segment, output [7:0]bits);

integer cnt,last_cnt;
reg state = 0;
reg last_state = 0;
reg [7:0] b = 8'b00000000;
assign segment = 1'b0;

initial
begin
 cnt = 0;
 last_cnt =0;
end

always@(posedge clock)
begin


 state = A;
        if (state != last_state)
            begin
                if (state != B)
                    cnt = cnt + 1;
                else
                    cnt = cnt - 1;
            end
        last_state = state;
        if(cnt!=last_cnt)
        b = 8'b11111111;
        else
        b = 8'b00000000;

        last_cnt = cnt;

end

assign bits = b;

endmodule