module pipelined_machine(clk, reset);
    input        clk, reset;

    wire [31:0]  PC;
    wire [31:2]  next_PC, PC_plus4, PC_target,PC_plus4_DE;
    wire [31:0]  inst, inst_DE;

    wire [31:0]  imm = {{ 16{inst_DE[15]} }, inst_DE[15:0] };  // sign-extended immediate
    wire [4:0]   rs = inst_DE[25:21];
    wire [4:0]   rt = inst_DE[20:16];
    wire [4:0]   rd = inst_DE[15:11];
    wire [5:0]   opcode = inst_DE[31:26];
    wire [5:0]   funct = inst_DE[5:0];

    wire [4:0]   wr_regnum, wr_regnum_MW;
    wire [2:0]   ALUOp;

    wire         RegWrite, BEQ, ALUSrc, MemRead, MemWrite, MemToReg, RegDst;
    wire         PCSrc, zero;
    wire [31:0]  rd1_data, rd2_data, B_data, alu_out_data, alu_pipelined, load_data, wr_data, pipeMuxOut, pipeMuxOut_MW, pipeMuxOut_A;
    wire         forwardA,forwardB, stalling, flushed, pipedRegWrite, pipedMemRead, pipedMemWrite, pipedMemToReg;


    // DO NOT comment out or rename this module
    // or the test bench will break
    register #(30, 30'h100000) PC_reg(PC[31:2], next_PC[31:2], clk, ~stalling, reset);

    assign PC[1:0] = 2'b0;  // bottom bits hard coded to 00
    adder30 next_PC_adder(PC_plus4, PC[31:2], 30'h1);
    adder30 target_PC_adder(PC_target, PC_plus4_DE, imm[29:0]);
    mux2v #(30) branch_mux(next_PC, PC_plus4, PC_target, PCSrc);
    assign PCSrc = BEQ & zero;

    // DO NOT comment out or rename this module
    // or the test bench will break
    instruction_memory imem(inst, PC[31:2]);

    mips_decode decode(ALUOp, RegWrite, BEQ, ALUSrc, MemRead, MemWrite, MemToReg, RegDst,
                      opcode, funct);

    // DO NOT comment out or rename this module
    // or the test bench will break
    regfile rf (rd1_data, rd2_data,
               rs, rt, wr_regnum_MW, wr_data,
               pipedRegWrite, clk, reset);

    mux2v #(32) imm_mux(B_data, pipeMuxOut, imm, ALUSrc);
    alu32 alu(alu_out_data, zero, ALUOp, pipeMuxOut_A, B_data);

    // DO NOT comment out or rename this module
    // or the test bench will break
    data_mem data_memory(load_data, alu_pipelined, pipeMuxOut_MW, pipedMemRead, pipedMemWrite, clk, reset);

    mux2v #(32) wb_mux(wr_data, alu_pipelined, load_data,pipedMemToReg);
    mux2v #(5) rd_mux(wr_regnum, rt, rd, RegDst);

    mux2v #(32) pipeOrRtMux(pipeMuxOut,rd2_data,alu_pipelined,forwardB);
    mux2v #(32) pipeOrRsMux(pipeMuxOut_A,rd1_data,alu_pipelined,forwardA);


    register #(30) ifdePCPLUSFOURpipe(PC_plus4_DE,PC_plus4,clk,~stalling,flushed);
    register #(32) ifdeINSTpipe(inst_DE,inst,clk,~stalling,flushed);
    register #(5) mwREGNUMpipe(wr_regnum_MW,wr_regnum,clk,1'b1,reset);
    register #(32) mwMUXOUTpipe(pipeMuxOut_MW,pipeMuxOut,clk,1'b1,reset);
    register #(32) mwALUpipe(alu_pipelined,alu_out_data,clk,1'b1,reset);

    register #(1) regWritePipe(pipedRegWrite,RegWrite,clk,1'b1,reset);
    register #(1) memToRegPipe(pipedMemToReg,MemToReg,clk,1'b1,reset);
    register #(1) memReadPipe(pipedMemRead,MemRead,clk,1'b1,reset);
    register #(1) memWritePipe(pipedMemWrite,MemWrite,clk,1'b1,reset);

    assign forwardA = pipedRegWrite & (wr_regnum_MW == rs) & (rs != 0);
    assign forwardB = pipedRegWrite & (wr_regnum_MW == rt) & (rt != 0);
    assign stalling = pipedMemRead & (forwardA | forwardB);
    assign flushed = reset | PCSrc;

endmodule // pipelined_machine