async fn raise_system_frequency(
    flash_acr: reg::flash::Acr<Srt>,
    rcc_cier: reg::rcc::Cier<Srt>,
    rcc_cicr: reg::rcc::Cicr<Srt>,
    rcc_cifr: reg::rcc::Cifr<Srt>,
    rcc_cr: reg::rcc::Cr<Srt>,
    rcc_cfgr: reg::rcc::Cfgr<Srt>,
    thr_rcc: thr::Rcc,
) {
    thr_rcc.enable_int();
    rcc_cier.modify(|r| r.set_hserdyie());

    // We need to move ownership of `hserdyc` and `hserdyf` into the fiber.
    let reg::rcc::Cifr {
        hserdyf, ..
    } = rcc_cifr;
    let reg::rcc::Cicr {
        hserdyc, ..
    } = rcc_cicr;

    // Attach a listener that will notify us when RCC_CIFR_HSERDYF is asserted.
    let hserdy = thr_rcc.add_future(fib::new_fn(move || {
        if hserdyf.read_bit() {
            hserdyc.set_bit();
            fib::Complete(())
        } else {
            fib::Yielded(())
        }
    }));
    // Enable the HSE clock.
    rcc_cr.modify(|r| r.set_hseon());
    // Sleep until RCC_CIR_HSERDYF is asserted.
    hserdy.await;

    // Two wait states, if 0 MHz < SYS_CLK <= 16 Mhz.
    flash_acr.modify(|r| r.write_latency(0));
    rcc_cfgr.modify(|r| r.write_sw(0b10)); // HSE selected as system clock
}