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  1.  
  2. module top(
  3.  
  4.     //////////// CLOCK //////////
  5.     input  CLOCK_50,
  6.     input  CLOCK_LOC,
  7.     output CLOCK_SYNC,
  8.     //input CLOCK_SYNC,
  9.        
  10.     //////////// SDRAM1 //////////
  11.     output [1:0] SDRAM1_BA,
  12.     output [12:0] SDRAM1_A,
  13.     output SDRAM1_CKE,
  14.     output SDRAM1_CLK,
  15.     output SDRAM1_CS,
  16.     output SDRAM1_CAS,
  17.     output SDRAM1_RAS,
  18.     output SDRAM1_WE,
  19.     output [1:0]  SDRAM1_DQM,
  20.     inout  [15:0] SDRAM1_D,
  21.    
  22.     //////////// SDRAM2 //////////
  23.     output [14:0] SDRAM2_A,
  24.     output SDRAM2_CKE,
  25.     output SDRAM2_CLK,
  26.     output SDRAM2_CS,
  27.     output SDRAM2_CAS,
  28.     output SDRAM2_RAS,
  29.     output SDRAM2_WE,
  30.     output [1:0]  SDRAM2_DQM,
  31.     inout  [15:0] SDRAM2_D,
  32.    
  33.     //////////// QBUS //////////
  34.     output          QB_DEN,
  35.     output reg [17:0]   QB_DIN,
  36.     output reg  QB_TCLK,
  37.    
  38.     output          QB_REN,
  39.     input  [17:0]   QB_ROUT,
  40.     input           QB_RCLK,
  41.    
  42.     //////////// CH1_IM //////////
  43.     input  [17:0] CH1_IM,
  44.     //////////// CH1_RE //////////
  45.     input  [17:0] CH1_RE,
  46.  
  47.     //////////// CH2_IM //////////
  48.     //input  [17:0] CH2_IM,
  49.     //////////// CH2_RE //////////
  50.     //input  [17:0] CH2_RE,
  51.  
  52.     input        CH1_RCLK,
  53.     output       CH1_REN,
  54.     input        CH2_RCLK,
  55.     output       CH2_REN,
  56.     /*input          CH3_RCLK,
  57.     output       CH3_REN,
  58.     input        CH4_RCLK,
  59.     output       CH4_REN,
  60.     input        CH5_RCLK,
  61.     output       CH5_REN,
  62.     input        CH6_RCLK,
  63.     output       CH6_REN,
  64.     input        CH7_RCLK,
  65.     output       CH7_REN,
  66.     input        CH8_RCLK,
  67.     output       CH8_REN,*/
  68.    
  69.     //////////// USB_FT //////////
  70.     input [7:0] USB_FT_ACBUS,
  71.    
  72.     input USB_FT_nRXF,
  73.     input USB_FT_nTXE,
  74.     input USB_FT_nRD,
  75.     output reg USB_FT_nWR,
  76.     input USB_FT_CLKIN,
  77.     output reg USB_FT_nOE = 1,
  78.     output [7:0] USB_FT_D,
  79.    
  80.     //////////// USB_FT //////////
  81.     //output         UC_CLK,
  82.     //output         UC_ALE,   
  83.     //output [7:0] UC_P0,
  84.     //output [7:0] UC_P1,
  85.     //output [7:0] UC_P2,
  86.     //output [7:0] UC_P3,  
  87.    
  88.     //////////// MAXV //////////   
  89.     //output    MAXV_SPI_SCK,
  90.     //input     MAXV_SPI_MISO,
  91.     //output    MAXV_SPI_MOSI, 
  92.     //output    MAXV_SPI_SS,
  93.    
  94.     //output    MAXV_CLOCK,
  95.     //input     MAXV_IRQ,  
  96.    
  97.        
  98.     //////////// MAXV //////////   
  99.     //output    I2C_CLK,
  100.     //inout     I2C_SDA,   
  101.        
  102.     //////////// CARU //////////   
  103.     //output    CARU_EN,
  104.    
  105.     //input     CARU_C_IN,
  106.     //input     CARU_D_IN,
  107.     //output    CARU_C_OUT,
  108.     //output    CARU_D_OUT,
  109.    
  110.     //////////// SPI //////////
  111.     //input     SPI_SCLK,  
  112.     //output    SPI_MISO,
  113.     //input     SPI_MOSI,
  114.     //input     SPI_CS,
  115.    
  116.     //input     DS,
  117.     //input     TI,
  118.    
  119.     //////////// SIGNALS //////////
  120.     //output X6_ENA,
  121.     //output X6_TAU_OBM,
  122.     //output X6_ISCHP,
  123.     //output X6_ISCHP_OP,
  124.     //output X6_KO,
  125.    
  126.     //////////// SIGNALS //////////
  127.     /*output X29_ENA,
  128.     input X24_IBP,
  129.     input X24_SYNTH_OK,
  130.     input X24_MFS_OK,*/
  131.    
  132.     //////////// CONN20 ////////// 
  133.     input CONN20_TIM1,
  134.     input CONN20_TIM2,
  135.     input CONN20_TIM3,
  136.     input CONN20_IZP,
  137.    
  138.    
  139.     //////////// SIGNALS //////////
  140.     //output PRD_OK,
  141.     //output VIP_OK,
  142.     //output TR_OK,
  143.     //output NADD1_OK,
  144.     //output MOD_OK,
  145.     //output P3_OK,
  146.     //output P1_OK,
  147.     //output POUT_OK,
  148.    
  149.     //////////// SIGNALS //////////
  150.     /*output X27_ENA,
  151.     input X27_ADC1_OL,
  152.     input X27_ADC2_OL,
  153.     input X27_ADC3_OL, 
  154.     input X27_ADC4_OL,
  155.  
  156.     input X27_ADC1_OK,
  157.     input X27_ADC2_OK,
  158.     input X27_ADC3_OK, 
  159.     input X27_ADC4_OK,
  160.    
  161.     input X27_SHU_OK,
  162.     input X27_PS_OK,
  163.     input X27_SOCHI_OK,
  164.     input X27_CARU_OK,
  165.     input X27_IP32_OK,
  166.    
  167.     input X27_DET41,
  168.     input X27_DET42,
  169.     input X27_DET43,
  170.     input X27_DET44,
  171.    
  172.     input X27_DET31,
  173.     input X27_DET32,
  174.     input X27_DET33,
  175.     input X27_DET34,
  176.    
  177.     input X27_DET21,
  178.     input X27_DET22,
  179.     input X27_DET23,
  180.     input X27_DET24,
  181.  
  182.     input X27_DET11,
  183.     input X27_DET12,
  184.     input X27_DET13,
  185.     input X27_DET14,*/
  186.    
  187.     //////////// SIGNALS //////////
  188.     //output X8_X11_ENA,
  189.     //output X8_IV,
  190.     //output X11_D0,
  191.    
  192.     //
  193.     output reg GPIO0,
  194.     output reg GPIO1
  195.  
  196.    
  197. );
  198.  
  199. reg [31:0] count = 0;
  200.  
  201. reg [1:0] ind = 0;
  202.  
  203. //assign GPIO0 = CLOCK_LOC; //USB_FT_CLKIN;
  204.  
  205. assign CLOCK_SYNC = 1;
  206.  
  207. assign QB_DEN = 1;
  208. assign QB_REN = 1;
  209.  
  210. assign CH2_REN = 1;
  211.  
  212. reg clkDelim;
  213.  
  214.  
  215. reg fifoUsbTxWrReq;
  216. //reg fifoUsbTxRdReq;
  217. wire fifoUsbTxRdEmpty;
  218. //wire fifoUsbTxRdReq = (USB_FT_nTXE==0)&&(fifoUsbTxRdEmpty==0);
  219. wire fifoUsbTxRdReq = (USB_FT_nTXE==0);
  220. wire fifoUsbTxWrFull;
  221.  
  222. //fifo_lv_rx fifoUsbTx(.data(dataIn), .wrclk(CLOCK_LOC), .wrreq(clkCnt[1]),
  223. //                      .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));
  224.  
  225. fifo_lv_rx fifoUsbTx(.data(fifoWrCnt), .wrclk(CLOCK_LOC), .wrreq(fifoUsbTxWrReq), .wrfull(fifoUsbTxWrFull),
  226.                         .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));
  227.  
  228.  
  229. //fifo_lv_rx fifoUsbTx(.data(QB_ROUT[15:0]), .wrclk(QB_RCLK), .wrreq(QB_RCLK),
  230. //                      .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));
  231.  
  232. //assign USB_FT_nWR = !((USB_FT_nTXE==0) &&(fifoUsbTxRdEmpty==0));                     
  233. always @(posedge USB_FT_CLKIN) begin
  234.     USB_FT_nWR <= !((USB_FT_nTXE==0) &&(fifoUsbTxRdEmpty==0));
  235. end
  236.  
  237.  
  238. always @(posedge USB_FT_CLKIN) begin
  239.  
  240.     //
  241.     //USB_FT_nWR <= USB_FT_nTXE;
  242.    
  243.    
  244.     if((USB_FT_nWR  == 0) && (USB_FT_nTXE == 0)) begin
  245.        
  246.         //USB_FT_D <= count>>(8*ind);
  247.         //USB_FT_D <= rClkCount;
  248.         //USB_FT_D <= dataIn;
  249.         //USB_FT_D <= count[7:0];
  250.         //USB_FT_D <= CH1_IM[7:0];
  251.         //USB_FT_D <= ch1ClkCnt[7:0];
  252.         //USB_FT_D <= CH1_RE[7:0];
  253.         //USB_FT_D <= CH1_RE>>(8*ind);
  254.        
  255.         //USB_FT_D <= dataIn>>(8*count[0]);
  256.        
  257.        
  258.        
  259.         count <= count + 1;
  260.         if(ind == 3) begin
  261.             ind <= 0;
  262.             //count <= count + 1;
  263.             //USB_FT_D <= ch2ClkCnt[7:0];
  264.         end
  265.         else begin
  266.             ind <= ind + 1;
  267.             //USB_FT_D <= ch1ClkCnt[7:0];
  268.         end
  269.        
  270.         if(count[0] == 0) begin
  271.             //USB_FT_D <= dataIn[7:0];
  272.         end
  273.         else begin
  274.             //USB_FT_D <= dataIn[15:8];
  275.         end
  276.        
  277.     end
  278.    
  279.    
  280.     //clkDelim <= !clkDelim ;
  281.     // <= clkDelim;
  282.    
  283.  
  284. end
  285.  
  286. reg [31:0] clockCounter;
  287. reg lastState = 0;
  288. reg [4:0] clkCnt;
  289.  
  290. reg [15:0] fifoWrCnt = 0;
  291. //assign GPIO0 = CLOCK_LOC;
  292. //assign QB_TCLK  = CLOCK_LOC;
  293. always @(posedge CLOCK_LOC) begin
  294.     GPIO0 <= !GPIO0;
  295.     QB_TCLK <= !QB_TCLK;
  296.     //QB_TCLK <= clkCnt[4];
  297.     clkCnt <= clkCnt + 1;
  298.    
  299.     clockCounter <= clockCounter + 1;
  300.    
  301.     //if((clockCounter[3] == 1) & (clockCounter[0] == 1)) begin
  302.     lastState <= clockCounter[3];
  303.     if((clockCounter[3] == 1) && (lastState == 0)) begin
  304.         GPIO1 <= 1;
  305.         fifoWrCnt <= fifoWrCnt + 1;
  306.         fifoUsbTxWrReq <= 1;
  307.     //  QB_TCLK <= 1;
  308.     end
  309.     else begin
  310.         fifoUsbTxWrReq <= 0;
  311.         GPIO1 <= 0;
  312. //      QB_TCLK <= 0;
  313.     end
  314. end
  315.  
  316. reg dataRecv = 0;
  317. reg [15:0] dataOut = 0;
  318.  
  319. reg [17:0] dataOutArr [5:0];
  320. always @(posedge QB_TCLK) begin
  321.     dataOut <= dataOut + 1;
  322.     QB_DIN <= dataOut;
  323.     dataRecv <= 1;
  324.     //QB_DIN <= 18'b000000000111111111;
  325. end
  326.  
  327.  
  328. reg [17:0] dataIn;
  329. reg [8:0] rClkCount = 0;
  330. always @(posedge QB_RCLK) begin
  331.     dataIn <= QB_ROUT;     
  332.     rClkCount <= rClkCount + 1;
  333. end
  334.  
  335.  
  336. always @(posedge CH2_RCLK) begin
  337.     //dataIn <= CH1_RE;
  338.    
  339. end
  340.  
  341.  
  342. reg [31:0] ch1ClkCnt = 0;
  343. always @(posedge CH1_RCLK) begin
  344.     //dataIn <= CH1_RE;
  345.     ch1ClkCnt <= ch1ClkCnt + 1;
  346.    
  347. end
  348.  
  349. reg [31:0] ch2ClkCnt = 0;
  350. always @(posedge CH2_RCLK) begin
  351.     //dataIn <= CH1_RE;
  352.     ch2ClkCnt <= ch2ClkCnt + 1;
  353.    
  354. end
  355.  
  356.  
  357.  
  358.  
  359. endmodule
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