module RIPPLECARRY(

    output wire Carry,
    output wire [7:0] Sum,
    input wire [7:0] A, B,
    input wire Cin

    );

    wire C0, C1, C2, C3, C4, C5, C6;

    FULLADDER FA0 (C0, Sum[0], A[0], B[0], Cin);
    FULLADDER FA1 (C1, Sum[1], A[1], B[1], C0);
    FULLADDER FA2 (C2, Sum[2], A[2], B[2], C1);
    FULLADDER FA3 (C3, Sum[3], A[3], B[3], C2);
    FULLADDER FA4 (C4, Sum[4], A[4], B[4], C3);
    FULLADDER FA5 (C5, Sum[5], A[5], B[5], C4);
    FULLADDER FA6 (C6, Sum[6], A[6], B[6], C5);
    FULLADDER FA7 (Carry, Sum[7], A[7], B[7], C6);

endmodule


module MUX2_1(

    output wire [7:0] F,
    input wire S,
    input wire [7:0] A, B

    );

    wire nS;
    wire [7:0] wA, wB;

    NOT NOT0 (nS, S);

    AND AND0 (wA[0], A[0], nS);
    AND AND1 (wA[1], A[1], nS);
    AND AND2 (wA[2], A[2], nS);
    AND AND3 (wA[3], A[3], nS);
    AND AND4 (wA[4], A[4], nS);
    AND AND5 (wA[5], A[5], nS);
    AND AND6 (wA[6], A[6], nS);
    AND AND7 (wA[7], A[7], nS);

    AND AND8 (wB[0], B[0], S);
    AND AND9 (wB[1], B[1], S);
    AND AND10 (wB[2], B[2], S);
    AND AND11 (wB[3], B[3], S);
    AND AND12 (wB[4], B[4], S);
    AND AND13 (wB[5], B[5], S);
    AND AND14 (wB[6], B[6], S);
    AND AND15 (wB[7], B[7], S);

    OR8 OR0 (F, wA, wB);

endmodule

module dflipflop (output reg Q,Qn,
                  input wire clk, res, EN, D);

  always @ (posedge clk or negedge res or negedge EN)
    begin
        if (!res)
            begin
                Q <= 1'b0;
                Qn <= 1'b1;
            end
        else if (!EN)
            begin
                Q <= 1'b1;
                Qn <= 1'b0;
            end
        else
            begin
                Q <= D;
                Qn <= ~D;
            end
    end

endmodule

/*-----------------------------------------------REGISTERS-----------------------------------------------*/

module reg8a (

    output wire [7:0] Reg_Out,
    input wire clk, res, EN,
    input wire [7:0] Reg_In

    );

    wire [7:0] nQ;
    wire [7:0] Mux_Out;

    MUX2_1 mux0 (Mux_Out, EN, Reg_Out, Reg_In);

    dflipflop dff0 (Reg_Out[0], nQ[1], clk, res, 1'b1, Mux_Out[0]);
    dflipflop dff1 (Reg_Out[1], nQ[0], clk, res, 1'b1, Mux_Out[1]);
    dflipflop dff2 (Reg_Out[2], nQ[3], clk, res, 1'b1, Mux_Out[2]);
    dflipflop dff3 (Reg_Out[3], nQ[2], clk, res, 1'b1, Mux_Out[3]);
    dflipflop dff4 (Reg_Out[4], nQ[5], clk, res, 1'b1, Mux_Out[4]);
    dflipflop dff5 (Reg_Out[5], nQ[4], clk, res, 1'b1, Mux_Out[5]);
    dflipflop dff6 (Reg_Out[6], nQ[7], clk, res, 1'b1, Mux_Out[6]);
    dflipflop dff7 (Reg_Out[7], nQ[6], clk, res, 1'b1, Mux_Out[7]);

endmodule

/*-----------------------------------------------COUNTER-----------------------------------------------*/

module count8a (

    output wire [7:0] CNT,
    input wire clk, res, EN, load,
    input wire [7:0] CNT_In

    );

    wire Cout;
    wire [7:0] Mux_Out;
    wire [7:0] Inc_Out;

    MUX2_1 mux0 (Mux_Out, load, Inc_Out, CNT_In);

    RIPPLECARRY adder0 (Cout, Inc_Out, CNT, 8'b00000001, 1'b0);

    reg8a reg0 (CNT, clk, res, EN, Mux_Out);

endmodule