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  1. Args: ./llc -debug -debug-node-output=id ../../../llvm/test/CodeGen/ARM/crash-shufflevector.ll
  2. Subtarget features: SSELevel 7, 3DNowLevel 0, 64bit 1
  3. Computing probabilities for
  4.  
  5.  
  6.  
  7. === f
  8. Initial selection DAG: BB#0 'f:'
  9. SelectionDAG has 23 nodes:
  10. Node0: ch = EntryToken [ORD=1]
  11.  
  12. Node1: v4i8 = undef [ORD=1]
  13.  
  14. Node2: v16i8 = undef
  15.  
  16. Node3: i32 = GlobalAddress<void (<16 x i8>)* @g> 0
  17.  
  18. Node4: i32 = TargetConstant<0> [ORD=4]
  19.  
  20. Node5: v16i8 = Register %XMM0 [ORD=4]
  21.  
  22. Node0: <multiple use>
  23. Node4: <multiple use>
  24. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4]
  25.  
  26. Node5: <multiple use>
  27. Node0: <multiple use>
  28. Node7: v4i32 = Register %vreg0 [ORD=1]
  29.  
  30. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1]
  31.  
  32. Node9: v4i8 = truncate Node8 [ORD=1]
  33.  
  34. Node1: <multiple use>
  35. Node1: <multiple use>
  36. Node1: <multiple use>
  37. Node10: v16i8 = concat_vectors Node9, Node1, Node1, Node1 [ORD=1]
  38.  
  39. Node0: <multiple use>
  40. Node11: v4i32 = Register %vreg1 [ORD=2]
  41.  
  42. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2]
  43.  
  44. Node13: v4i8 = truncate Node12 [ORD=2]
  45.  
  46. Node1: <multiple use>
  47. Node1: <multiple use>
  48. Node1: <multiple use>
  49. Node14: v16i8 = concat_vectors Node13, Node1, Node1, Node1 [ORD=2]
  50.  
  51. Node15: v16i8 = vector_shuffle Node10, Node14<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3]
  52.  
  53. Node16: ch,glue = CopyToReg Node6, Node5, Node15 [ORD=4]
  54.  
  55. Node16: <multiple use>
  56. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
  57.  
  58. Node5: <multiple use>
  59. Node18: Untyped = RegisterMask [ORD=4]
  60.  
  61. Node16: <multiple use>
  62. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4]
  63.  
  64. Node19: <multiple use>
  65. Node4: <multiple use>
  66. Node4: <multiple use>
  67. Node19: <multiple use>
  68. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4]
  69.  
  70. Node21: i16 = TargetConstant<0>
  71.  
  72. Node22: ch = X86ISD::RET_FLAG Node20, Node21
  73.  
  74.  
  75. Optimized lowered selection DAG: BB#0 'f:'
  76. SelectionDAG has 21 nodes:
  77. Node0: ch = EntryToken [ORD=1]
  78.  
  79. Node1: v4i8 = undef [ORD=1]
  80.  
  81. Node4: i32 = TargetConstant<0> [ORD=4]
  82.  
  83. Node5: v16i8 = Register %XMM0 [ORD=4]
  84.  
  85. Node0: <multiple use>
  86. Node4: <multiple use>
  87. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4]
  88.  
  89. Node5: <multiple use>
  90. Node0: <multiple use>
  91. Node7: v4i32 = Register %vreg0 [ORD=1]
  92.  
  93. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1]
  94.  
  95. Node9: v4i8 = truncate Node8 [ORD=1]
  96.  
  97. Node1: <multiple use>
  98. Node1: <multiple use>
  99. Node1: <multiple use>
  100. Node10: v16i8 = concat_vectors Node9, Node1, Node1, Node1 [ORD=1]
  101.  
  102. Node0: <multiple use>
  103. Node11: v4i32 = Register %vreg1 [ORD=2]
  104.  
  105. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2]
  106.  
  107. Node13: v4i8 = truncate Node12 [ORD=2]
  108.  
  109. Node1: <multiple use>
  110. Node1: <multiple use>
  111. Node1: <multiple use>
  112. Node14: v16i8 = concat_vectors Node13, Node1, Node1, Node1 [ORD=2]
  113.  
  114. Node15: v16i8 = vector_shuffle Node10, Node14<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3]
  115.  
  116. Node16: ch,glue = CopyToReg Node6, Node5, Node15 [ORD=4]
  117.  
  118. Node16: <multiple use>
  119. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
  120.  
  121. Node5: <multiple use>
  122. Node18: Untyped = RegisterMask [ORD=4]
  123.  
  124. Node16: <multiple use>
  125. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4]
  126.  
  127. Node19: <multiple use>
  128. Node4: <multiple use>
  129. Node4: <multiple use>
  130. Node19: <multiple use>
  131. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4]
  132.  
  133. Node21: i16 = TargetConstant<0>
  134.  
  135. Node22: ch = X86ISD::RET_FLAG Node20, Node21
  136.  
  137.  
  138. Legally typed node: Node21: i16 = TargetConstant<0> [ID=0]
  139.  
  140. Legally typed node: Node18: Untyped = RegisterMask [ORD=4] [ID=0]
  141.  
  142. Legally typed node: Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=0]
  143.  
  144. Legally typed node: Node5: v16i8 = Register %XMM0 [ORD=4] [ID=0]
  145.  
  146. Legally typed node: Node4: i32 = TargetConstant<0> [ORD=4] [ID=0]
  147.  
  148. Promote integer result: Node1: v4i8 = undef [ORD=1] [ID=0]
  149.  
  150. Legally typed node: Node2: v4i32 = undef [ID=0]
  151.  
  152. Legally typed node: Node11: v4i32 = Register %vreg1 [ORD=2] [ID=0]
  153.  
  154. Legally typed node: Node7: v4i32 = Register %vreg0 [ORD=1] [ID=0]
  155.  
  156. Legally typed node: Node0: ch = EntryToken [ORD=1] [ID=0]
  157.  
  158. Legally typed node: Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=0]
  159.  
  160. Promote integer result: Node9: v4i8 = truncate Node8 [ORD=1] [ID=0]
  161.  
  162. Promote integer operand: Node10: v16i8 = concat_vectors Node9, Node1, Node1, Node1 [ORD=1] [ID=0]
  163.  
  164. Legally typed node: Node23: i8 = undef [ID=0]
  165.  
  166. Legally typed node: Node24: i32 = Constant<3> [ID=0]
  167.  
  168. Legally typed node: Node25: i32 = extract_vector_elt Node8, Node24 [ID=0]
  169.  
  170. Legally typed node: Node26: i8 = truncate Node25 [ID=0]
  171.  
  172. Legally typed node: Node27: i32 = Constant<2> [ID=0]
  173.  
  174. Legally typed node: Node28: i32 = extract_vector_elt Node8, Node27 [ID=0]
  175.  
  176. Legally typed node: Node29: i8 = truncate Node28 [ID=0]
  177.  
  178. Legally typed node: Node30: i32 = Constant<1> [ID=0]
  179.  
  180. Legally typed node: Node31: i32 = extract_vector_elt Node8, Node30 [ID=0]
  181.  
  182. Legally typed node: Node32: i8 = truncate Node31 [ID=0]
  183.  
  184. Legally typed node: Node3: i32 = Constant<0> [ID=0]
  185.  
  186. Legally typed node: Node33: i32 = extract_vector_elt Node8, Node3 [ID=0]
  187.  
  188. Legally typed node: Node34: i8 = truncate Node33 [ID=0]
  189.  
  190. Legally typed node: Node35: v16i8 = BUILD_VECTOR Node34, Node32, Node29, Node26, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=0]
  191.  
  192. Legally typed node: Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=0]
  193.  
  194. Promote integer result: Node13: v4i8 = truncate Node12 [ORD=2] [ID=0]
  195.  
  196. Promote integer operand: Node14: v16i8 = concat_vectors Node13, Node1, Node1, Node1 [ORD=2] [ID=0]
  197.  
  198. Legally typed node: Node36: i32 = extract_vector_elt Node12, Node24 [ID=0]
  199.  
  200. Legally typed node: Node37: i8 = truncate Node36 [ID=0]
  201.  
  202. Legally typed node: Node38: i32 = extract_vector_elt Node12, Node27 [ID=0]
  203.  
  204. Legally typed node: Node39: i8 = truncate Node38 [ID=0]
  205.  
  206. Legally typed node: Node40: i32 = extract_vector_elt Node12, Node30 [ID=0]
  207.  
  208. Legally typed node: Node41: i8 = truncate Node40 [ID=0]
  209.  
  210. Legally typed node: Node42: i32 = extract_vector_elt Node12, Node3 [ID=0]
  211.  
  212. Legally typed node: Node43: i8 = truncate Node42 [ID=0]
  213.  
  214. Legally typed node: Node44: v16i8 = BUILD_VECTOR Node43, Node41, Node39, Node37, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=0]
  215.  
  216. Legally typed node: Node15: v16i8 = vector_shuffle Node35, Node44<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=0]
  217.  
  218. Legally typed node: Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=0]
  219.  
  220. Legally typed node: Node16: ch,glue = CopyToReg Node6, Node5, Node15 [ORD=4] [ID=0]
  221.  
  222. Legally typed node: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=0]
  223.  
  224. Legally typed node: Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=0]
  225.  
  226. Legally typed node: Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=0]
  227.  
  228. Legally typed node: Node45: ch = handlenode Node22 [ID=0]
  229.  
  230. Type-legalized selection DAG: BB#0 'f:'
  231. SelectionDAG has 39 nodes:
  232. Node0: ch = EntryToken [ORD=1] [ID=-3]
  233.  
  234. Node0: <multiple use>
  235. Node7: v4i32 = Register %vreg0 [ORD=1] [ID=-3]
  236.  
  237. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=-3]
  238.  
  239. Node0: <multiple use>
  240. Node11: v4i32 = Register %vreg1 [ORD=2] [ID=-3]
  241.  
  242. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=-3]
  243.  
  244. Node4: i32 = TargetConstant<0> [ORD=4] [ID=-3]
  245.  
  246. Node5: v16i8 = Register %XMM0 [ORD=4] [ID=-3]
  247.  
  248. Node0: <multiple use>
  249. Node4: <multiple use>
  250. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=-3]
  251.  
  252. Node5: <multiple use>
  253. Node8: <multiple use>
  254. Node3: <multiple use>
  255. Node33: i32 = extract_vector_elt Node8, Node3 [ID=-3]
  256.  
  257. Node34: i8 = truncate Node33 [ID=-3]
  258.  
  259. Node8: <multiple use>
  260. Node30: <multiple use>
  261. Node31: i32 = extract_vector_elt Node8, Node30 [ID=-3]
  262.  
  263. Node32: i8 = truncate Node31 [ID=-3]
  264.  
  265. Node8: <multiple use>
  266. Node27: <multiple use>
  267. Node28: i32 = extract_vector_elt Node8, Node27 [ID=-3]
  268.  
  269. Node29: i8 = truncate Node28 [ID=-3]
  270.  
  271. Node8: <multiple use>
  272. Node24: <multiple use>
  273. Node25: i32 = extract_vector_elt Node8, Node24 [ID=-3]
  274.  
  275. Node26: i8 = truncate Node25 [ID=-3]
  276.  
  277. Node23: <multiple use>
  278. Node23: <multiple use>
  279. Node23: <multiple use>
  280. Node23: <multiple use>
  281. Node23: <multiple use>
  282. Node23: <multiple use>
  283. Node23: <multiple use>
  284. Node23: <multiple use>
  285. Node23: <multiple use>
  286. Node23: <multiple use>
  287. Node23: <multiple use>
  288. Node23: <multiple use>
  289. Node35: v16i8 = BUILD_VECTOR Node34, Node32, Node29, Node26, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=-3]
  290.  
  291. Node12: <multiple use>
  292. Node3: <multiple use>
  293. Node42: i32 = extract_vector_elt Node12, Node3 [ID=-3]
  294.  
  295. Node43: i8 = truncate Node42 [ID=-3]
  296.  
  297. Node12: <multiple use>
  298. Node30: <multiple use>
  299. Node40: i32 = extract_vector_elt Node12, Node30 [ID=-3]
  300.  
  301. Node41: i8 = truncate Node40 [ID=-3]
  302.  
  303. Node12: <multiple use>
  304. Node27: <multiple use>
  305. Node38: i32 = extract_vector_elt Node12, Node27 [ID=-3]
  306.  
  307. Node39: i8 = truncate Node38 [ID=-3]
  308.  
  309. Node12: <multiple use>
  310. Node24: <multiple use>
  311. Node36: i32 = extract_vector_elt Node12, Node24 [ID=-3]
  312.  
  313. Node37: i8 = truncate Node36 [ID=-3]
  314.  
  315. Node23: <multiple use>
  316. Node23: <multiple use>
  317. Node23: <multiple use>
  318. Node23: <multiple use>
  319. Node23: <multiple use>
  320. Node23: <multiple use>
  321. Node23: <multiple use>
  322. Node23: <multiple use>
  323. Node23: <multiple use>
  324. Node23: <multiple use>
  325. Node23: <multiple use>
  326. Node23: <multiple use>
  327. Node44: v16i8 = BUILD_VECTOR Node43, Node41, Node39, Node37, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=-3]
  328.  
  329. Node15: v16i8 = vector_shuffle Node35, Node44<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=-3]
  330.  
  331. Node16: ch,glue = CopyToReg Node6, Node5, Node15 [ORD=4] [ID=-3]
  332.  
  333. Node16: <multiple use>
  334. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=-3]
  335.  
  336. Node5: <multiple use>
  337. Node18: Untyped = RegisterMask [ORD=4] [ID=-3]
  338.  
  339. Node16: <multiple use>
  340. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=-3]
  341.  
  342. Node3: i32 = Constant<0> [ID=-3]
  343.  
  344. Node30: i32 = Constant<1> [ID=-3]
  345.  
  346. Node27: i32 = Constant<2> [ID=-3]
  347.  
  348. Node24: i32 = Constant<3> [ID=-3]
  349.  
  350. Node23: i8 = undef [ID=-3]
  351.  
  352. Node19: <multiple use>
  353. Node4: <multiple use>
  354. Node4: <multiple use>
  355. Node19: <multiple use>
  356. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=-3]
  357.  
  358. Node21: i16 = TargetConstant<0> [ID=-3]
  359.  
  360. Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=-3]
  361.  
  362.  
  363.  
  364. Replacing.3 Node37: i8 = truncate Node36 [ID=-3]
  365.  
  366. With: Node10: i8 = extract_vector_elt Node9, Node1
  367.  
  368.  
  369. Replacing.3 Node39: i8 = truncate Node38 [ID=-3]
  370.  
  371. With: Node37: i8 = extract_vector_elt Node9, Node36
  372.  
  373.  
  374. Replacing.3 Node41: i8 = truncate Node40 [ID=-3]
  375.  
  376. With: Node39: i8 = extract_vector_elt Node9, Node38
  377.  
  378.  
  379. Replacing.3 Node43: i8 = truncate Node42 [ID=-3]
  380.  
  381. With: Node40: i8 = extract_vector_elt Node9, Node3
  382.  
  383.  
  384. Replacing.3 Node44: v16i8 = BUILD_VECTOR Node40, Node39, Node37, Node10, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=-3]
  385.  
  386. With: Node43: v16i8 = vector_shuffle Node9, Node42<0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
  387.  
  388.  
  389. Replacing.3 Node26: i8 = truncate Node25 [ID=-3]
  390.  
  391. With: Node39: i8 = extract_vector_elt Node40, Node38
  392.  
  393.  
  394. Replacing.3 Node29: i8 = truncate Node28 [ID=-3]
  395.  
  396. With: Node25: i8 = extract_vector_elt Node40, Node24
  397.  
  398.  
  399. Replacing.3 Node32: i8 = truncate Node31 [ID=-3]
  400.  
  401. With: Node28: i8 = extract_vector_elt Node40, Node27
  402.  
  403.  
  404. Replacing.3 Node34: i8 = truncate Node33 [ID=-3]
  405.  
  406. With: Node30: i8 = extract_vector_elt Node40, Node3
  407.  
  408.  
  409. Replacing.3 Node35: v16i8 = BUILD_VECTOR Node30, Node28, Node25, Node39, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23, Node23 [ID=-3]
  410.  
  411. With: Node33: v16i8 = vector_shuffle Node40, Node42<0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
  412.  
  413. Optimized type-legalized selection DAG: BB#0 'f:'
  414. SelectionDAG has 21 nodes:
  415. Node0: ch = EntryToken [ORD=1] [ID=-3]
  416.  
  417. Node4: i32 = TargetConstant<0> [ORD=4] [ID=-3]
  418.  
  419. Node5: v16i8 = Register %XMM0 [ORD=4] [ID=-3]
  420.  
  421. Node0: <multiple use>
  422. Node4: <multiple use>
  423. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=-3]
  424.  
  425. Node5: <multiple use>
  426. Node0: <multiple use>
  427. Node7: v4i32 = Register %vreg0 [ORD=1] [ID=-3]
  428.  
  429. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=-3]
  430.  
  431. Node40: v16i8 = bitcast Node8
  432.  
  433. Node42: <multiple use>
  434. Node33: v16i8 = vector_shuffle Node40, Node42<0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
  435.  
  436. Node0: <multiple use>
  437. Node11: v4i32 = Register %vreg1 [ORD=2] [ID=-3]
  438.  
  439. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=-3]
  440.  
  441. Node9: v16i8 = bitcast Node12
  442.  
  443. Node42: <multiple use>
  444. Node43: v16i8 = vector_shuffle Node9, Node42<0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
  445.  
  446. Node15: v16i8 = vector_shuffle Node33, Node43<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=-3]
  447.  
  448. Node16: ch,glue = CopyToReg Node6, Node5, Node15 [ORD=4] [ID=-3]
  449.  
  450. Node16: <multiple use>
  451. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=-3]
  452.  
  453. Node5: <multiple use>
  454. Node18: Untyped = RegisterMask [ORD=4] [ID=-3]
  455.  
  456. Node16: <multiple use>
  457. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=-3]
  458.  
  459. Node42: v16i8 = undef
  460.  
  461. Node19: <multiple use>
  462. Node4: <multiple use>
  463. Node4: <multiple use>
  464. Node19: <multiple use>
  465. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=-3]
  466.  
  467. Node21: i16 = TargetConstant<0> [ID=-3]
  468.  
  469. Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=-3]
  470.  
  471.  
  472. Legalized selection DAG: BB#0 'f:'
  473. SelectionDAG has 30 nodes:
  474. Node0: ch = EntryToken [ORD=1] [ID=0]
  475.  
  476. Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
  477.  
  478. Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
  479.  
  480. Node0: <multiple use>
  481. Node4: <multiple use>
  482. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=11]
  483.  
  484. Node5: <multiple use>
  485. Node3: <multiple use>
  486. Node3: <multiple use>
  487. Node0: <multiple use>
  488. Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
  489.  
  490. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=10]
  491.  
  492. Node9: v16i8 = bitcast Node12 [ID=13]
  493.  
  494. Node39: <multiple use>
  495. Node34: v16i8 = X86ISD::PSHUFB Node9, Node39
  496.  
  497. Node30: v4i32 = bitcast Node34
  498.  
  499. Node25: v4i32 = X86ISD::MOVSS Node3, Node30
  500.  
  501. Node27: i8 = Constant<36>
  502.  
  503. Node38: v4i32 = X86ISD::SHUFP Node3, Node25, Node27
  504.  
  505. Node28: v16i8 = bitcast Node38
  506.  
  507. Node16: ch,glue = CopyToReg Node6, Node5, Node28 [ORD=4] [ID=17]
  508.  
  509. Node16: <multiple use>
  510. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
  511.  
  512. Node5: <multiple use>
  513. Node18: Untyped = RegisterMask [ORD=4] [ID=6]
  514.  
  515. Node16: <multiple use>
  516. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=18]
  517.  
  518. Node0: <multiple use>
  519. Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
  520.  
  521. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  522.  
  523. Node40: v16i8 = bitcast Node8 [ID=12]
  524.  
  525. Node39: <multiple use>
  526. Node43: v16i8 = X86ISD::PSHUFB Node40, Node39
  527.  
  528. Node3: v4i32 = bitcast Node43
  529.  
  530. Node0: <multiple use>
  531. Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
  532.  
  533. Node23: i32 = X86ISD::Wrapper Node31
  534.  
  535. Node33: i32 = undef
  536.  
  537. Node24: v2i64,ch = load Node0, Node23, Node33<LD16[ConstantPool]>
  538.  
  539. Node39: v16i8 = bitcast Node24
  540.  
  541. Node19: <multiple use>
  542. Node4: <multiple use>
  543. Node4: <multiple use>
  544. Node19: <multiple use>
  545. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=19]
  546.  
  547. Node21: i16 = TargetConstant<0> [ID=7]
  548.  
  549. Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=20]
  550.  
  551.  
  552. Optimized legalized selection DAG: BB#0 'f:'
  553. SelectionDAG has 30 nodes:
  554. Node0: ch = EntryToken [ORD=1] [ID=0]
  555.  
  556. Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
  557.  
  558. Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
  559.  
  560. Node0: <multiple use>
  561. Node4: <multiple use>
  562. Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=11]
  563.  
  564. Node5: <multiple use>
  565. Node3: <multiple use>
  566. Node3: <multiple use>
  567. Node0: <multiple use>
  568. Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
  569.  
  570. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=10]
  571.  
  572. Node9: v16i8 = bitcast Node12 [ID=13]
  573.  
  574. Node39: <multiple use>
  575. Node34: v16i8 = X86ISD::PSHUFB Node9, Node39
  576.  
  577. Node30: v4i32 = bitcast Node34
  578.  
  579. Node25: v4i32 = X86ISD::MOVSS Node3, Node30
  580.  
  581. Node27: i8 = Constant<36>
  582.  
  583. Node38: v4i32 = X86ISD::SHUFP Node3, Node25, Node27
  584.  
  585. Node28: v16i8 = bitcast Node38
  586.  
  587. Node16: ch,glue = CopyToReg Node6, Node5, Node28 [ORD=4] [ID=17]
  588.  
  589. Node16: <multiple use>
  590. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
  591.  
  592. Node5: <multiple use>
  593. Node18: Untyped = RegisterMask [ORD=4] [ID=6]
  594.  
  595. Node16: <multiple use>
  596. Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=18]
  597.  
  598. Node0: <multiple use>
  599. Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
  600.  
  601. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  602.  
  603. Node40: v16i8 = bitcast Node8 [ID=12]
  604.  
  605. Node39: <multiple use>
  606. Node43: v16i8 = X86ISD::PSHUFB Node40, Node39
  607.  
  608. Node3: v4i32 = bitcast Node43
  609.  
  610. Node0: <multiple use>
  611. Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
  612.  
  613. Node23: i32 = X86ISD::Wrapper Node31
  614.  
  615. Node33: i32 = undef
  616.  
  617. Node24: v2i64,ch = load Node0, Node23, Node33<LD16[ConstantPool]>
  618.  
  619. Node39: v16i8 = bitcast Node24
  620.  
  621. Node19: <multiple use>
  622. Node4: <multiple use>
  623. Node4: <multiple use>
  624. Node19: <multiple use>
  625. Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=19]
  626.  
  627. Node21: i16 = TargetConstant<0> [ID=7]
  628.  
  629. Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=20]
  630.  
  631.  
  632. ===== Instruction selection begins: BB#0 ''
  633. Selecting: Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=29]
  634.  
  635. ISEL: Starting pattern match on root node: Node22: ch = X86ISD::RET_FLAG Node20, Node21 [ID=29]
  636.  
  637. Morphed node: Node22: ch = RET Node20
  638.  
  639. ISEL: Match complete!
  640. => Node22: ch = RET Node20
  641.  
  642. Selecting: Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=28]
  643.  
  644. ISEL: Starting pattern match on root node: Node20: ch,glue = callseq_end Node19, Node4, Node4, Node19:1 [ORD=4] [ID=28]
  645.  
  646. Initial Opcode index to 82627
  647. Morphed node: Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4]
  648.  
  649. ISEL: Match complete!
  650. => Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4]
  651.  
  652. Selecting: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=27]
  653.  
  654. ISEL: Starting pattern match on root node: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5, Node18, Node16:1 [ORD=4] [ID=27]
  655.  
  656. Initial Opcode index to 65628
  657. Match failed at index 65634
  658. Continuing at 65695
  659. OpcodeSwitch from 65701 to 65705
  660. TypeSwitch[i32] from 65705 to 65719
  661. Morphed node: Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4]
  662.  
  663. ISEL: Match complete!
  664. => Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4]
  665.  
  666. Selecting: Node16: ch,glue = CopyToReg Node6, Node5, Node28 [ORD=4] [ID=26]
  667.  
  668. => Node16: ch,glue = CopyToReg Node6, Node5, Node28 [ORD=4]
  669.  
  670. Selecting: Node28: v16i8 = bitcast Node38 [ID=25]
  671.  
  672. ISEL: Starting pattern match on root node: Node28: v16i8 = bitcast Node38 [ID=25]
  673.  
  674. Initial Opcode index to 80865
  675. Match failed at index 80869
  676. Continuing at 80895
  677. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  678. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  679. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  680. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  681. Match failed at index 80898
  682. Continuing at 81030
  683. Match failed at index 81033
  684. Continuing at 81137
  685. Match failed at index 81139
  686. Continuing at 81213
  687. Match failed at index 81216
  688. Continuing at 81334
  689. TypeSwitch[v16i8] from 81341 to 81358
  690. ISEL: Match complete!
  691. => Node28: v16i8 = bitcast Node38 [ID=25]
  692.  
  693. Selecting: Node38: v4i32 = X86ISD::SHUFP Node3, Node25, Node27 [ID=24]
  694.  
  695. ISEL: Starting pattern match on root node: Node38: v4i32 = X86ISD::SHUFP Node3, Node25, Node27 [ID=24]
  696.  
  697. Initial Opcode index to 101465
  698. Match failed at index 101471
  699. Continuing at 101692
  700. TypeSwitch[v4i32] from 101703 to 101706
  701. Skipped scope entry (due to false predicate) at index 101708, continuing at 101722
  702. Morphed node: Node38: v4i32 = SHUFPSrri Node3, Node25, Node28
  703.  
  704. ISEL: Match complete!
  705. => Node38: v4i32 = SHUFPSrri Node3, Node25, Node28
  706.  
  707. Selecting: Node25: v4i32 = X86ISD::MOVSS Node3, Node30 [ID=23]
  708.  
  709. ISEL: Starting pattern match on root node: Node25: v4i32 = X86ISD::MOVSS Node3, Node30 [ID=23]
  710.  
  711. Initial Opcode index to 115181
  712. TypeSwitch[v4i32] from 115185 to 115188
  713. Skipped scope entry (due to false predicate) at index 115190, continuing at 115213
  714. Created node: Node21: f32 = COPY_TO_REGCLASS Node30, Node27
  715.  
  716. Morphed node: Node25: v4i32 = MOVSSrr Node3, Node21
  717.  
  718. ISEL: Match complete!
  719. => Node25: v4i32 = MOVSSrr Node3, Node21
  720.  
  721. Selecting: Node30: v4i32 = bitcast Node34 [ID=22]
  722.  
  723. ISEL: Starting pattern match on root node: Node30: v4i32 = bitcast Node34 [ID=22]
  724.  
  725. Initial Opcode index to 80865
  726. Match failed at index 80869
  727. Continuing at 80895
  728. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  729. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  730. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  731. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  732. Match failed at index 80898
  733. Continuing at 81030
  734. Match failed at index 81033
  735. Continuing at 81137
  736. Match failed at index 81139
  737. Continuing at 81213
  738. Match failed at index 81216
  739. Continuing at 81334
  740. Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
  741. Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
  742. TypeSwitch[v4i32] from 81421 to 81431
  743. ISEL: Match complete!
  744. => Node30: v4i32 = bitcast Node34 [ID=22]
  745.  
  746. Selecting: Node3: v4i32 = bitcast Node43 [ID=21]
  747.  
  748. ISEL: Starting pattern match on root node: Node3: v4i32 = bitcast Node43 [ID=21]
  749.  
  750. Initial Opcode index to 80865
  751. Match failed at index 80869
  752. Continuing at 80895
  753. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  754. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  755. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  756. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  757. Match failed at index 80898
  758. Continuing at 81030
  759. Match failed at index 81033
  760. Continuing at 81137
  761. Match failed at index 81139
  762. Continuing at 81213
  763. Match failed at index 81216
  764. Continuing at 81334
  765. Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
  766. Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
  767. TypeSwitch[v4i32] from 81421 to 81431
  768. ISEL: Match complete!
  769. => Node3: v4i32 = bitcast Node43 [ID=21]
  770.  
  771. Selecting: Node34: v16i8 = X86ISD::PSHUFB Node9, Node39 [ID=20]
  772.  
  773. ISEL: Starting pattern match on root node: Node34: v16i8 = X86ISD::PSHUFB Node9, Node39 [ID=20]
  774.  
  775. Initial Opcode index to 110519
  776. Match failed at index 110534
  777. Continuing at 110617
  778. TypeSwitch[v16i8] from 110619 to 110622
  779. Skipped scope entry (due to false predicate) at index 110624, continuing at 110635
  780. Morphed node: Node34: v16i8 = PSHUFBrr Node9, Node39
  781.  
  782. ISEL: Match complete!
  783. => Node34: v16i8 = PSHUFBrr Node9, Node39
  784.  
  785. Selecting: Node43: v16i8 = X86ISD::PSHUFB Node40, Node39 [ID=19]
  786.  
  787. ISEL: Starting pattern match on root node: Node43: v16i8 = X86ISD::PSHUFB Node40, Node39 [ID=19]
  788.  
  789. Initial Opcode index to 110519
  790. Match failed at index 110534
  791. Continuing at 110617
  792. TypeSwitch[v16i8] from 110619 to 110622
  793. Skipped scope entry (due to false predicate) at index 110624, continuing at 110635
  794. Morphed node: Node43: v16i8 = PSHUFBrr Node40, Node39
  795.  
  796. ISEL: Match complete!
  797. => Node43: v16i8 = PSHUFBrr Node40, Node39
  798.  
  799. Selecting: Node39: v16i8 = bitcast Node24 [ID=18]
  800.  
  801. ISEL: Starting pattern match on root node: Node39: v16i8 = bitcast Node24 [ID=18]
  802.  
  803. Initial Opcode index to 80865
  804. Match failed at index 80869
  805. Continuing at 80895
  806. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  807. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  808. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  809. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  810. Match failed at index 80898
  811. Continuing at 81030
  812. Match failed at index 81041
  813. Continuing at 81137
  814. Match failed at index 81139
  815. Continuing at 81213
  816. Match failed at index 81216
  817. Continuing at 81334
  818. Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
  819. Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
  820. Skipped scope entry (due to false predicate) at index 81419, continuing at 81458
  821. Skipped scope entry (due to false predicate) at index 81459, continuing at 81498
  822. Skipped scope entry (due to false predicate) at index 81499, continuing at 81538
  823. TypeSwitch[v16i8] from 81541 to 81558
  824. ISEL: Match complete!
  825. => Node39: v16i8 = bitcast Node24 [ID=18]
  826.  
  827. Selecting: Node24: v2i64,ch = load Node0, Node23, Node33<LD16[ConstantPool]> [ID=17]
  828.  
  829. ISEL: Starting pattern match on root node: Node24: v2i64,ch = load Node0, Node23, Node33<LD16[ConstantPool]> [ID=17]
  830.  
  831. Initial Opcode index to 75053
  832. Match failed at index 75065
  833. Continuing at 75083
  834. Match failed at index 75086
  835. Continuing at 75104
  836. Match failed at index 75107
  837. Continuing at 75125
  838. Match failed at index 75128
  839. Continuing at 75146
  840. Match failed at index 75147
  841. Continuing at 75191
  842. Match failed at index 75192
  843. Continuing at 75236
  844. Match failed at index 75237
  845. Continuing at 75300
  846. Match failed at index 75301
  847. Continuing at 75364
  848. Match failed at index 75367
  849. Continuing at 75387
  850. Match failed at index 75388
  851. Continuing at 75466
  852. Match failed at index 75468
  853. Continuing at 75693
  854. Match failed at index 75694
  855. Continuing at 75728
  856. Match failed at index 75729
  857. Continuing at 75763
  858. Continuing at 75764
  859. Match failed at index 75773
  860. Continuing at 75795
  861. Match failed at index 75804
  862. Continuing at 75908
  863. Match failed at index 75909
  864. Continuing at 75980
  865. Match failed at index 75984
  866. Continuing at 76115
  867. Match failed at index 76116
  868. Continuing at 76235
  869. TypeSwitch[v2i64] from 76239 to 76242
  870. Match failed at index 76246
  871. Continuing at 76264
  872. Skipped scope entry (due to false predicate) at index 76267, continuing at 76285
  873. MatchAddress: X86ISelAddressMode 0xbf92c6f0
  874. Base_Reg nul Base.FrameIndex 0
  875. Scale1
  876. IndexReg nul Disp 0
  877. GV nul CP nul
  878. ES nul JT-1 Align0
  879. Morphed node: Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]>
  880.  
  881. ISEL: Match complete!
  882. => Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]>
  883.  
  884. Selecting: Node9: v16i8 = bitcast Node12 [ID=16]
  885.  
  886. ISEL: Starting pattern match on root node: Node9: v16i8 = bitcast Node12 [ID=16]
  887.  
  888. Initial Opcode index to 80865
  889. Match failed at index 80869
  890. Continuing at 80895
  891. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  892. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  893. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  894. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  895. Match failed at index 80898
  896. Continuing at 81030
  897. Match failed at index 81033
  898. Continuing at 81137
  899. Match failed at index 81139
  900. Continuing at 81213
  901. Match failed at index 81216
  902. Continuing at 81334
  903. TypeSwitch[v16i8] from 81341 to 81358
  904. ISEL: Match complete!
  905. => Node9: v16i8 = bitcast Node12 [ID=16]
  906.  
  907. Selecting: Node40: v16i8 = bitcast Node8 [ID=15]
  908.  
  909. ISEL: Starting pattern match on root node: Node40: v16i8 = bitcast Node8 [ID=15]
  910.  
  911. Initial Opcode index to 80865
  912. Match failed at index 80869
  913. Continuing at 80895
  914. Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
  915. Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
  916. Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
  917. Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
  918. Match failed at index 80898
  919. Continuing at 81030
  920. Match failed at index 81033
  921. Continuing at 81137
  922. Match failed at index 81139
  923. Continuing at 81213
  924. Match failed at index 81216
  925. Continuing at 81334
  926. TypeSwitch[v16i8] from 81341 to 81358
  927. ISEL: Match complete!
  928. => Node40: v16i8 = bitcast Node8 [ID=15]
  929.  
  930. Selecting: Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=13]
  931.  
  932. ISEL: Starting pattern match on root node: Node6: ch,glue = callseq_start Node0, Node4 [ORD=4] [ID=13]
  933.  
  934. Initial Opcode index to 84589
  935. Morphed node: Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4]
  936.  
  937. ISEL: Match complete!
  938. => Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4]
  939.  
  940. Selecting: Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=12]
  941.  
  942. => Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2]
  943.  
  944. Selecting: Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=11]
  945.  
  946. => Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1]
  947.  
  948. Selecting: Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0 [ID=10]
  949.  
  950. => Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
  951.  
  952. Selecting: Node18: Untyped = RegisterMask [ORD=4] [ID=6]
  953.  
  954. => Node18: Untyped = RegisterMask [ORD=4]
  955.  
  956. Selecting: Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
  957.  
  958. => Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
  959.  
  960. Selecting: Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
  961.  
  962. => Node5: v16i8 = Register %XMM0 [ORD=4]
  963.  
  964. Selecting: Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
  965.  
  966. => Node4: i32 = TargetConstant<0> [ORD=4]
  967.  
  968. Selecting: Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
  969.  
  970. => Node11: v4i32 = Register %vreg1 [ORD=2]
  971.  
  972. Selecting: Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
  973.  
  974. => Node7: v4i32 = Register %vreg0 [ORD=1]
  975.  
  976. Selecting: Node0: ch = EntryToken [ORD=1] [ID=0]
  977.  
  978. => Node0: ch = EntryToken [ORD=1]
  979.  
  980. ===== Instruction selection ends:
  981. Selected selection DAG: BB#0 'f:'
  982. SelectionDAG has 25 nodes:
  983. Node0: ch = EntryToken [ORD=1]
  984.  
  985. Node4: i32 = TargetConstant<0> [ORD=4]
  986.  
  987. Node5: v16i8 = Register %XMM0 [ORD=4]
  988.  
  989. Node39: <multiple use>
  990. Node3: i8 = TargetConstant<1>
  991.  
  992. Node39: <multiple use>
  993. Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
  994.  
  995. Node39: <multiple use>
  996. Node0: <multiple use>
  997. Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]>
  998.  
  999. Node0: <multiple use>
  1000. Node7: v4i32 = Register %vreg0 [ORD=1]
  1001.  
  1002. Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1]
  1003.  
  1004. Node24: <multiple use>
  1005. Node43: v16i8 = PSHUFBrr Node8, Node24
  1006.  
  1007. Node4: <multiple use>
  1008. Node0: <multiple use>
  1009. Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4]
  1010.  
  1011. Node5: <multiple use>
  1012. Node43: <multiple use>
  1013. Node43: <multiple use>
  1014. Node0: <multiple use>
  1015. Node11: v4i32 = Register %vreg1 [ORD=2]
  1016.  
  1017. Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2]
  1018.  
  1019. Node24: <multiple use>
  1020. Node34: v16i8 = PSHUFBrr Node12, Node24
  1021.  
  1022. Node27: i32 = TargetConstant<9>
  1023.  
  1024. Node21: f32 = COPY_TO_REGCLASS Node34, Node27
  1025.  
  1026. Node25: v4i32 = MOVSSrr Node43, Node21
  1027.  
  1028. Node28: i8 = TargetConstant<36>
  1029.  
  1030. Node38: v4i32 = SHUFPSrri Node43, Node25, Node28
  1031.  
  1032. Node16: ch,glue = CopyToReg Node6:1, Node5, Node38 [ORD=4]
  1033.  
  1034. Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
  1035.  
  1036. Node5: <multiple use>
  1037. Node18: Untyped = RegisterMask [ORD=4]
  1038.  
  1039. Node16: <multiple use>
  1040. Node16: <multiple use>
  1041. Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4]
  1042.  
  1043. Node39: i32 = Register %noreg
  1044.  
  1045. Node4: <multiple use>
  1046. Node4: <multiple use>
  1047. Node19: <multiple use>
  1048. Node19: <multiple use>
  1049. Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4]
  1050.  
  1051. Node22: ch = RET Node20:1
  1052.  
  1053.  
  1054. ********** List Scheduling BB#0 '' **********
  1055. SU(0): Node22: ch = RET Node20:1 [ID=0]
  1056.  
  1057. # preds left : 1
  1058. # succs left : 0
  1059. # rdefs left : 0
  1060. Latency : 1
  1061. Depth : 0
  1062. Height : 0
  1063. Predecessors:
  1064. ch SU(1): Latency=1
  1065.  
  1066. SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4] [ID=1]
  1067.  
  1068. Node16: ch,glue = CopyToReg Node6:1, Node5, Node38 [ORD=4] [ID=1]
  1069.  
  1070. Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4] [ID=1]
  1071.  
  1072. # preds left : 2
  1073. # succs left : 1
  1074. # rdefs left : 0
  1075. Latency : 1
  1076. Depth : 0
  1077. Height : 0
  1078. Predecessors:
  1079. ch SU(10): Latency=1
  1080. val SU(2): Latency=1
  1081. Successors:
  1082. ch SU(0): Latency=1
  1083.  
  1084. SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, Node28 [ID=2]
  1085.  
  1086. # preds left : 2
  1087. # succs left : 1
  1088. # rdefs left : 1
  1089. Latency : 1
  1090. Depth : 0
  1091. Height : 0
  1092. Predecessors:
  1093. val SU(8): Latency=1
  1094. val SU(3): Latency=1
  1095. Successors:
  1096. val SU(1): Latency=1
  1097.  
  1098. SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
  1099.  
  1100. # preds left : 2
  1101. # succs left : 1
  1102. # rdefs left : 1
  1103. Latency : 1
  1104. Depth : 0
  1105. Height : 0
  1106. Predecessors:
  1107. val SU(8): Latency=1
  1108. val SU(4): Latency=1
  1109. Successors:
  1110. val SU(2): Latency=1
  1111.  
  1112. SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, Node27 [ID=4]
  1113.  
  1114. # preds left : 1
  1115. # succs left : 1
  1116. # rdefs left : 1
  1117. Latency : 1
  1118. Depth : 0
  1119. Height : 0
  1120. Predecessors:
  1121. val SU(5): Latency=1
  1122. Successors:
  1123. val SU(3): Latency=1
  1124.  
  1125. SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
  1126.  
  1127. # preds left : 2
  1128. # succs left : 1
  1129. # rdefs left : 1
  1130. Latency : 1
  1131. Depth : 0
  1132. Height : 0
  1133. Predecessors:
  1134. val SU(7): Latency=1
  1135. val SU(6): Latency=1
  1136. Successors:
  1137. val SU(4): Latency=1
  1138.  
  1139. SU(6): Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]> [ID=6]
  1140.  
  1141. # preds left : 0
  1142. # succs left : 2
  1143. # rdefs left : 1
  1144. Latency : 1
  1145. Depth : 0
  1146. Height : 0
  1147. Successors:
  1148. val SU(5): Latency=1
  1149. val SU(8): Latency=1
  1150.  
  1151. SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=7]
  1152.  
  1153. # preds left : 0
  1154. # succs left : 1
  1155. # rdefs left : 1
  1156. Latency : 1
  1157. Depth : 0
  1158. Height : 0
  1159. Successors:
  1160. val SU(5): Latency=1
  1161.  
  1162. SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1163.  
  1164. # preds left : 2
  1165. # succs left : 2
  1166. # rdefs left : 1
  1167. Latency : 1
  1168. Depth : 0
  1169. Height : 0
  1170. Predecessors:
  1171. val SU(9): Latency=1
  1172. val SU(6): Latency=1
  1173. Successors:
  1174. val SU(2): Latency=1
  1175. val SU(3): Latency=1
  1176.  
  1177. SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  1178.  
  1179. # preds left : 0
  1180. # succs left : 1
  1181. # rdefs left : 1
  1182. Latency : 1
  1183. Depth : 0
  1184. Height : 0
  1185. Successors:
  1186. val SU(8): Latency=1
  1187.  
  1188. SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4] [ID=10]
  1189.  
  1190. # preds left : 0
  1191. # succs left : 1
  1192. # rdefs left : 0
  1193. Latency : 1
  1194. Depth : 0
  1195. Height : 0
  1196. Successors:
  1197. ch SU(1): Latency=1
  1198.  
  1199.  
  1200. Examining Available:
  1201. Height 0: SU(0): Node22: ch = RET Node20:1 [ID=0]
  1202.  
  1203.  
  1204. *** Scheduling [0]: SU(0): Node22: ch = RET Node20:1 [ID=0]
  1205.  
  1206.  
  1207. Examining Available:
  1208. Height 1: SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4] [ID=1]
  1209.  
  1210. Node16: ch,glue = CopyToReg Node6:1, Node5, Node38 [ORD=4] [ID=1]
  1211.  
  1212. Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4] [ID=1]
  1213.  
  1214.  
  1215. *** Scheduling [1]: SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4] [ID=1]
  1216.  
  1217. Node16: ch,glue = CopyToReg Node6:1, Node5, Node38 [ORD=4] [ID=1]
  1218.  
  1219. Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4] [ID=1]
  1220.  
  1221.  
  1222. Examining Available:
  1223. Height 2: SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4] [ID=10]
  1224.  
  1225. Height 2: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, Node28 [ID=2]
  1226.  
  1227.  
  1228. *** Scheduling [2]: SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4] [ID=10]
  1229.  
  1230.  
  1231. Examining Available:
  1232. Height 2: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, Node28 [ID=2]
  1233.  
  1234.  
  1235. *** Scheduling [3]: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, Node28 [ID=2]
  1236.  
  1237.  
  1238. Examining Available:
  1239. Height 4: SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
  1240.  
  1241.  
  1242. *** Scheduling [4]: SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
  1243.  
  1244.  
  1245. Examining Available:
  1246. Height 5: SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, Node27 [ID=4]
  1247.  
  1248. Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1249.  
  1250.  
  1251. *** Scheduling [5]: SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, Node27 [ID=4]
  1252.  
  1253.  
  1254. Examining Available:
  1255. Height 6: SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
  1256.  
  1257. Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1258.  
  1259.  
  1260. *** Scheduling [6]: SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
  1261.  
  1262.  
  1263. Examining Available:
  1264. Height 7: SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=7]
  1265.  
  1266. Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1267.  
  1268.  
  1269. *** Scheduling [7]: SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=7]
  1270.  
  1271.  
  1272. Examining Available:
  1273. Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1274.  
  1275.  
  1276. *** Scheduling [8]: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1277.  
  1278.  
  1279. Examining Available:
  1280. Height 9: SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  1281.  
  1282. Height 9: SU(6): Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]> [ID=6]
  1283.  
  1284.  
  1285. *** Scheduling [9]: SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  1286.  
  1287.  
  1288. Examining Available:
  1289. Height 9: SU(6): Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]> [ID=6]
  1290.  
  1291.  
  1292. *** Scheduling [10]: SU(6): Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]> [ID=6]
  1293.  
  1294. *** Final schedule ***
  1295. SU(6): Node24: v2i64,ch = MOVAPSrm Node39, Node3, Node39, Node31, Node39, Node0<Mem:LD16[ConstantPool]> [ID=6]
  1296.  
  1297. SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7 [ORD=1] [ID=9]
  1298.  
  1299. SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
  1300.  
  1301. SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11 [ORD=2] [ID=7]
  1302.  
  1303. SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
  1304.  
  1305. SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, Node27 [ID=4]
  1306.  
  1307. SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
  1308.  
  1309. SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, Node28 [ID=2]
  1310.  
  1311. SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 Node4, Node0 [ORD=4] [ID=10]
  1312.  
  1313. SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 Node4, Node4, Node19, Node19:1 [ORD=4] [ID=1]
  1314.  
  1315. Node16: ch,glue = CopyToReg Node6:1, Node5, Node38 [ORD=4] [ID=1]
  1316.  
  1317. Node19: ch,glue = CALLpcrel32 Node17, Node5, Node18, Node16, Node16:1 [ORD=4] [ID=1]
  1318.  
  1319. SU(0): Node22: ch = RET Node20:1 [ID=0]
  1320.  
  1321.  
  1322. Total amount of phi nodes to update: 0
  1323. # Machine code for function f: SSA
  1324. Constant Pool:
  1325. cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
  1326. Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
  1327.  
  1328. 0B BB#0: derived from LLVM BB %0
  1329. Live Ins: %XMM0 %XMM1
  1330. 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
  1331. 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
  1332. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1333. 64B %vreg3<def,tied1> = PSHUFBrr %vreg0<tied0>, %vreg2; VR128:%vreg3,%vreg0,%vreg2
  1334. 80B %vreg4<def,tied1> = PSHUFBrr %vreg1<tied0>, %vreg2; VR128:%vreg4,%vreg1,%vreg2
  1335. 96B %vreg5<def> = COPY %vreg4; FR32:%vreg5 VR128:%vreg4
  1336. 112B %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg5<kill>; VR128:%vreg6,%vreg3 FR32:%vreg5
  1337. 128B %vreg7<def,tied1> = SHUFPSrri %vreg3<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg3,%vreg6
  1338. 144B ADJCALLSTACKDOWN32 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1339. 160B %XMM0<def> = COPY %vreg7; VR128:%vreg7
  1340. 176B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
  1341. 192B ADJCALLSTACKUP32 0, 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1342. 208B RET
  1343.  
  1344. # End machine code for function f.
  1345.  
  1346. ********** Stack Coloring **********
  1347. ********** Function: f
  1348. ******** Pre-regalloc Machine LICM: f ********
  1349. Entering:
  1350. Coalescing: %vreg5<def> = COPY %vreg4; FR32:%vreg5 VR128:%vreg4
  1351. *** to: %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg5<kill>; VR128:%vreg6,%vreg3 FR32:%vreg5
  1352. Exiting:
  1353. ******** Machine Sinking ********
  1354. ********** PROCESS IMPLICIT DEFS **********
  1355. ********** Function: f
  1356. ********** REWRITING TWO-ADDR INSTRS **********
  1357. ********** Function: f
  1358. %vreg3<def,tied1> = PSHUFBrr %vreg0<kill,tied0>, %vreg2; VR128:%vreg3,%vreg0,%vreg2
  1359. prepend: %vreg3<def> = COPY %vreg0; VR128:%vreg3,%vreg0
  1360. rewrite to: %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
  1361. %vreg4<def,tied1> = PSHUFBrr %vreg1<kill,tied0>, %vreg2<kill>; VR128:%vreg4,%vreg1,%vreg2
  1362. prepend: %vreg4<def> = COPY %vreg1; VR128:%vreg4,%vreg1
  1363. rewrite to: %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1364. %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg3,%vreg4
  1365. prepend: %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
  1366. rewrite to: %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1367. %vreg7<def,tied1> = SHUFPSrri %vreg3<kill,tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg3,%vreg6
  1368. prepend: %vreg7<def> = COPY %vreg3; VR128:%vreg7,%vreg3
  1369. rewrite to: %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1370. # Machine code for function f: Post SSA
  1371. Constant Pool:
  1372. cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
  1373. Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
  1374.  
  1375. 0B BB#0: derived from LLVM BB %0
  1376. Live Ins: %XMM0 %XMM1
  1377. 16B %vreg1<def> = COPY %XMM1<kill>; VR128:%vreg1
  1378. 32B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0
  1379. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1380. 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
  1381. 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
  1382. 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
  1383. 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1384. 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
  1385. 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1386. 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
  1387. 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1388. 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1389. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1390. 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use,kill>, %ESP<imp-def>
  1391. 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1392. 256B RET
  1393.  
  1394. # End machine code for function f.
  1395.  
  1396. ********** COMPUTING LIVE INTERVALS **********
  1397. ********** Function: f
  1398. BB#0: # derived from
  1399. 16B %vreg1<def> = COPY %XMM1<kill>; VR128:%vreg1
  1400. register: %vreg1 +[16r,96r:0)
  1401. 32B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0
  1402. register: %vreg0 +[32r,64r:0)
  1403. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1404. register: %vreg2 +[48r,112r:0)
  1405. 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
  1406. register: %vreg3 +[64r,160r:0)
  1407. 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
  1408. register: %vreg3 replace range with [64r,80r:1) RESULT: [64r,80r:1)[80r,160r:0) 0@80r 1@64r
  1409. 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
  1410. register: %vreg4 +[96r,144r:0)
  1411. 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1412. register: %vreg4 replace range with [96r,112r:1) RESULT: [96r,112r:1)[112r,144r:0) 0@112r 1@96r
  1413. 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
  1414. register: %vreg6 +[128r,176r:0)
  1415. 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1416. register: %vreg6 replace range with [128r,144r:1) RESULT: [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1417. 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
  1418. register: %vreg7 +[160r,208r:0)
  1419. 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1420. register: %vreg7 replace range with [160r,176r:1) RESULT: [160r,176r:1)[176r,208r:0) 0@176r 1@160r
  1421. 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1422. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1423. 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use,kill>, %ESP<imp-def>
  1424. 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1425. 256B RET
  1426. Computing live-in reg-units in ABI blocks.
  1427. 0B BB#0 XMM0#0 XMM1#0
  1428. Created 2 new intervals.
  1429. ********** INTERVALS **********
  1430. XMM0 = [0B,32r:0)[208r,224r:1) 0@0B-phi 1@208r
  1431. XMM1 = [0B,16r:0) 0@0B-phi
  1432. %vreg0 = [32r,64r:0) 0@32r
  1433. %vreg1 = [16r,96r:0) 0@16r
  1434. %vreg2 = [48r,112r:0) 0@48r
  1435. %vreg3 = [64r,80r:1)[80r,160r:0) 0@80r 1@64r
  1436. %vreg4 = [96r,112r:1)[112r,144r:0) 0@112r 1@96r
  1437. %vreg6 = [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1438. %vreg7 = [160r,176r:1)[176r,208r:0) 0@176r 1@160r
  1439. ********** MACHINEINSTRS **********
  1440. # Machine code for function f: Post SSA
  1441. Constant Pool:
  1442. cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
  1443. Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
  1444.  
  1445. 0B BB#0: derived from LLVM BB %0
  1446. Live Ins: %XMM0 %XMM1
  1447. 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
  1448. 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
  1449. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1450. 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
  1451. 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
  1452. 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
  1453. 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1454. 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
  1455. 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1456. 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
  1457. 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1458. 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1459. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1460. 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
  1461. 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1462. 256B RET
  1463.  
  1464. # End machine code for function f.
  1465.  
  1466. ********** COMPUTING LIVE DEBUG VARIABLES: f **********
  1467. ********** DEBUG VARIABLES **********
  1468. ********** SIMPLE REGISTER COALESCING **********
  1469. ********** Function: f
  1470. ********** JOINING INTERVALS ***********
  1471. :
  1472. 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
  1473. Considering merging %vreg1 with %XMM1
  1474. Can only merge into reserved registers.
  1475. 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
  1476. Considering merging %vreg0 with %XMM0
  1477. Can only merge into reserved registers.
  1478. 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
  1479. Considering merging to VR128 with %vreg0 in %vreg3
  1480. RHS = %vreg0 [32r,64r:0) 0@32r
  1481. LHS = %vreg3 [64r,80r:1)[80r,160r:0) 0@80r 1@64r
  1482. erased: 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
  1483. AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 ]
  1484. updated: 32B %vreg3<def> = COPY %XMM0; VR128:%vreg3
  1485. Joined. Result = %vreg3[32r,80r:1)[80r,160r:0) 0@80r 1@32r
  1486. 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
  1487. Considering merging to VR128 with %vreg1 in %vreg4
  1488. RHS = %vreg1 [16r,96r:0) 0@16r
  1489. LHS = %vreg4 [96r,112r:1)[112r,144r:0) 0@112r 1@96r
  1490. erased: 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
  1491. updated: 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
  1492. Joined. Result = %vreg4[16r,112r:1)[112r,144r:0) 0@112r 1@16r
  1493. 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
  1494. Considering merging to VR128 with %vreg3 in %vreg6
  1495. RHS = %vreg3 [32r,80r:1)[80r,160r:0) 0@80r 1@32r
  1496. LHS = %vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1497. Interference!
  1498. 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
  1499. Considering merging to VR128 with %vreg3 in %vreg7
  1500. RHS = %vreg3 [32r,80r:1)[80r,160r:0) 0@80r 1@32r
  1501. LHS = %vreg7 [160r,176r:1)[176r,208r:0) 0@176r 1@160r
  1502. erased: 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
  1503. updated: 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
  1504. updated: 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<tied0>, %vreg2; VR128:%vreg7,%vreg2
  1505. updated: 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
  1506. Joined. Result = %vreg7[32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
  1507. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1508. Considering merging %vreg7 with %XMM0
  1509. Can only merge into reserved registers.
  1510. 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
  1511. Considering merging to VR128 with %vreg7 in %vreg6
  1512. RHS = %vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1513. LHS = %vreg7 [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
  1514. Interference!
  1515. Trying to inflate 0 regs.
  1516. ********** INTERVALS **********
  1517. XMM0 = [0B,32r:0)[208r,224r:1) 0@0B-phi 1@208r
  1518. XMM1 = [0B,16r:0) 0@0B-phi
  1519. %vreg2 = [48r,112r:0) 0@48r
  1520. %vreg4 = [16r,112r:1)[112r,144r:0) 0@112r 1@16r
  1521. %vreg6 = [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1522. %vreg7 = [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
  1523. ********** MACHINEINSTRS **********
  1524. # Machine code for function f: Post SSA
  1525. Constant Pool:
  1526. cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
  1527. Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
  1528.  
  1529. 0B BB#0: derived from LLVM BB %0
  1530. Live Ins: %XMM0 %XMM1
  1531. 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
  1532. 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
  1533. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1534. 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<tied0>, %vreg2; VR128:%vreg7,%vreg2
  1535. 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1536. 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
  1537. 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1538. 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1539. 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1540. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1541. 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
  1542. 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1543. 256B RET
  1544.  
  1545. # End machine code for function f.
  1546.  
  1547. ********** DEBUG VARIABLES **********
  1548. ********** Compute Spill Weights **********
  1549. ********** Function: f
  1550. ********** GREEDY REGISTER ALLOCATION **********
  1551. ********** Function: f
  1552.  
  1553. selectOrSplit VR128:%vreg7 [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
  1554. AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 ]
  1555. assigning %vreg7 to %XMM0: XMM0
  1556.  
  1557. selectOrSplit VR128:%vreg4 [16r,112r:1)[112r,144r:0) 0@112r 1@16r
  1558. assigning %vreg4 to %XMM1: XMM1
  1559.  
  1560. selectOrSplit VR128:%vreg2 [48r,112r:0) 0@48r
  1561. assigning %vreg2 to %XMM2: XMM2
  1562.  
  1563. selectOrSplit VR128:%vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
  1564. assigning %vreg6 to %XMM2: XMM2
  1565. ********** REWRITE VIRTUAL REGISTERS **********
  1566. ********** Function: f
  1567. ********** REGISTER MAP **********
  1568. [%vreg2 -> %XMM2] VR128
  1569. [%vreg4 -> %XMM1] VR128
  1570. [%vreg6 -> %XMM2] VR128
  1571. [%vreg7 -> %XMM0] VR128
  1572.  
  1573. 0B BB#0: derived from LLVM BB %0
  1574. Live Ins: %XMM0 %XMM1
  1575. 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
  1576. 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
  1577. 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
  1578. 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<kill,tied0>, %vreg2; VR128:%vreg7,%vreg2
  1579. 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<kill,tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
  1580. 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
  1581. 144B %vreg6<def,tied1> = MOVSSrr %vreg6<kill,tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
  1582. 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<kill,tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
  1583. 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1584. 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
  1585. 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
  1586. 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1587. 256B RET
  1588. > %XMM1<def> = COPY %XMM1
  1589. Deleting identity copy.
  1590. > %XMM0<def> = COPY %XMM0
  1591. Deleting identity copy.
  1592. > %XMM2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool]
  1593. > %XMM0<def,tied1> = PSHUFBrr %XMM0<kill,tied0>, %XMM2
  1594. > %XMM1<def,tied1> = PSHUFBrr %XMM1<kill,tied0>, %XMM2<kill>
  1595. > %XMM2<def> = COPY %XMM0
  1596. > %XMM2<def,tied1> = MOVSSrr %XMM2<kill,tied0>, %XMM1<kill>
  1597. > %XMM0<def,tied1> = SHUFPSrri %XMM0<kill,tied0>, %XMM2<kill>, 36
  1598. > ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1599. > %XMM0<def> = COPY %XMM0<kill>
  1600. Deleting identity copy.
  1601. > CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
  1602. > ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
  1603. > RET
  1604. ********** EMITTING LIVE DEBUG VARIABLES **********
  1605. ********** Stack Slot Coloring **********
  1606. ********** Function: f
  1607. ******** Post-regalloc Machine LICM: f ********
  1608.  
  1609. Setting up live-ins for BB#0 derived from .
  1610. Block has no FP live-ins.
  1611.  
  1612. FPInst: RET
  1613. Stack contents:
  1614. Inserted instructions:
  1615. RET
  1616. Stack contents:
  1617. Machine Function
  1618. ********** EXPANDING POST-RA PSEUDO INSTRS **********
  1619. ********** Function: f
  1620. real copy: %XMM2<def> = COPY %XMM0
  1621. replaced by: %XMM2<def> = MOVAPSrr %XMM0
  1622. RPO[BB#0 derived from LLVM BB ] = 1
  1623. POT: BB#0 derived from LLVM BB
  1624. doLoop(BB#0 derived from LLVM BB , BB#0 derived from LLVM BB )
  1625. doBlock(BB#0 derived from LLVM BB )
  1626. Frequency(BB#0 derived from LLVM BB ) = 0
  1627. Frequency(BB#0 derived from LLVM BB ) = 1024
  1628. ********** FIX EXECUTION DEPENDENCIES: VR128 **********
  1629. BB#0: entry
  1630. XMM2: 2 %XMM2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool]
  1631. XMM0: 3 %XMM0<def,tied1> = PSHUFBrr %XMM0<kill,tied0>, %XMM2
  1632. XMM1: 4 %XMM1<def,tied1> = PSHUFBrr %XMM1<kill,tied0>, %XMM2<kill>
  1633. XMM2: 5 %XMM2<def> = MOVDQArr %XMM0
  1634. XMM2: 6 %XMM2<def,tied1> = MOVSSrr %XMM2<kill,tied0>, %XMM1<kill>
  1635. XMM0: 7 %XMM0<def,tied1> = SHUFPSrri %XMM0<kill,tied0>, %XMM2<kill>, 36
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