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  1. ' Gambas module file
  2.  
  3. ' The module was written by vuott from http://www.gambas-it.org/
  4. ' http://www.gambas-it.org/smf/index.php?action=profile;u=402
  5. Library "libcpuid:14.0.0"
  6.  
  7. Private Enum CPU_HINT_SSE_SIZE_AUTH = 0, NUM_CPU_HINTS
  8.  
  9. Private Enum CPU_FEATURE_FPU,
  10.              CPU_FEATURE_VME,
  11.              CPU_FEATURE_DE,
  12.              CPU_FEATURE_PSE,
  13.              CPU_FEATURE_TSC,
  14.              CPU_FEATURE_MSR,
  15.              CPU_FEATURE_PAE,
  16.              CPU_FEATURE_MCE, '!< Machine check exception */
  17.              CPU_FEATURE_CX8, '!< CMPXCHG8B instruction supported */
  18.              CPU_FEATURE_APIC, '!< APIC support */
  19.              CPU_FEATURE_MTRR, '!< Memory type range registers */
  20.              CPU_FEATURE_SEP, '!< SYSENTER / SYSEXIT instructions supported */
  21.              CPU_FEATURE_PGE, '!< Page global enable */
  22.              CPU_FEATURE_MCA, '!< Machine check architecture */
  23.              CPU_FEATURE_CMOV, '!< CMOVxx instructions supported */
  24.              CPU_FEATURE_PAT, '!< Page attribute table */
  25.              CPU_FEATURE_PSE36, '!< 36-bit page address extension */
  26.              CPU_FEATURE_PN,    '!< Processor serial # implemented (Intel P3 only) */
  27.              CPU_FEATURE_CLFLUSH, '!< CLFLUSH instruction supported */
  28.              CPU_FEATURE_DTS, '!< Debug store supported */
  29.              CPU_FEATURE_ACPI, '!< ACPI support (power states) */
  30.              CPU_FEATURE_MMX, '!< MMX instruction set supported */
  31.              CPU_FEATURE_FXSR, '!< FXSAVE / FXRSTOR supported */
  32.              CPU_FEATURE_SSE, '!< Streaming-SIMD Extensions (SSE) supported */
  33.              CPU_FEATURE_SSE2, '!< SSE2 instructions supported */
  34.              CPU_FEATURE_SS,        '!< Self-snoop */
  35.              CPU_FEATURE_HT,        '!< Hyper-threading supported (but might be disabled) */
  36.              CPU_FEATURE_TM,        '!< Thermal monitor */
  37.              CPU_FEATURE_IA64, '!< IA64 supported (Itanium only) */
  38.              CPU_FEATURE_PBE, '!< Pending-break enable */
  39.              CPU_FEATURE_PNI, '!< PNI (SSE3) instructions supported */
  40.              CPU_FEATURE_PCLMUL, '!< PCLMULQDQ instruction supported */
  41.              CPU_FEATURE_DTS64, '!< 64-bit Debug store supported */
  42.              CPU_FEATURE_MONITOR, '!< MONITOR / MWAIT supported */
  43.              CPU_FEATURE_DS_CPL, '!< CPL Qualified Debug Store */
  44.              CPU_FEATURE_VMX, '!< Virtualization technology supported */
  45.              CPU_FEATURE_SMX, '!< Safer mode exceptions */
  46.              CPU_FEATURE_EST, '!< Enhanced SpeedStep */
  47.              CPU_FEATURE_TM2, '!< Thermal monitor 2 */
  48.              CPU_FEATURE_SSSE3, '!< SSSE3 instructionss supported (this is different from SSE3!) */
  49.              CPU_FEATURE_CID, '!< Context ID supported */
  50.              CPU_FEATURE_CX16, '!< CMPXCHG16B instruction supported */
  51.              CPU_FEATURE_XTPR, '!< Send Task Priority Messages disable */
  52.              CPU_FEATURE_PDCM, '!< Performance capabilities MSR supported */
  53.              CPU_FEATURE_DCA, '!< Direct cache access supported */
  54.              CPU_FEATURE_SSE4_1, '!< SSE 4.1 instructions supported */
  55.              CPU_FEATURE_SSE4_2, '!< SSE 4.2 instructions supported */
  56.              CPU_FEATURE_SYSCALL, '!< SYSCALL / SYSRET instructions supported */
  57.              CPU_FEATURE_XD,    '!< Execute disable bit supported */
  58.              CPU_FEATURE_MOVBE, '!< MOVBE instruction supported */
  59.              CPU_FEATURE_POPCNT, '!< POPCNT instruction supported */
  60.              CPU_FEATURE_AES, '!< AES* instructions supported */
  61.              CPU_FEATURE_XSAVE, '!< XSAVE/XRSTOR/etc instructions supported */
  62.              CPU_FEATURE_OSXSAVE, '!< non-privileged copy of OSXSAVE supported */
  63.              CPU_FEATURE_AVX, '!< Advanced vector extensions supported */
  64.              CPU_FEATURE_MMXEXT, '!< AMD MMX-extended instructions supported */
  65.              CPU_FEATURE_3DNOW, '!< AMD 3DNow! instructions supported */
  66.              CPU_FEATURE_3DNOWEXT, '!< AMD 3DNow! extended instructions supported */
  67.              CPU_FEATURE_NX,        '!< No-execute bit supported */
  68.              CPU_FEATURE_FXSR_OPT, '!< FFXSR: FXSAVE and FXRSTOR optimizations */
  69.              CPU_FEATURE_RDTSCP, '!< RDTSCP instruction supported (AMD-only) */
  70.              CPU_FEATURE_LM,        '!< Long mode (x86_64/EM64T) supported */
  71.              CPU_FEATURE_LAHF_LM, '!< LAHF/SAHF supported in 64-bit mode */
  72.              CPU_FEATURE_CMP_LEGACY, '!< core multi-processing legacy mode */
  73.              CPU_FEATURE_SVM, '!< AMD Secure virtual machine */
  74.              CPU_FEATURE_ABM, '!< LZCNT instruction support */
  75.              CPU_FEATURE_MISALIGNSSE, '!< Misaligned SSE supported */
  76.              CPU_FEATURE_SSE4A, '!< SSE 4a from AMD */
  77.              CPU_FEATURE_3DNOWPREFETCH, '!< PREFETCH/PREFETCHW support */
  78.              CPU_FEATURE_OSVW, '!< OS Visible Workaround (AMD) */
  79.              CPU_FEATURE_IBS, '!< Instruction-based sampling */
  80.              CPU_FEATURE_SSE5, '!< SSE 5 instructions supported (deprecated, will never be 1) */
  81.              CPU_FEATURE_SKINIT, '!< SKINIT / STGI supported */
  82.              CPU_FEATURE_WDT, '!< Watchdog timer support */
  83.              CPU_FEATURE_TS,        '!< Temperature sensor */
  84.              CPU_FEATURE_FID, '!< Frequency ID control */
  85.              CPU_FEATURE_VID, '!< Voltage ID control */
  86.              CPU_FEATURE_TTP, '!< THERMTRIP */
  87.              CPU_FEATURE_TM_AMD, '!< AMD-specified hardware thermal control */
  88.              CPU_FEATURE_STC, '!< Software thermal control */
  89.              CPU_FEATURE_100MHZSTEPS, '!< 100 MHz multiplier control */
  90.              CPU_FEATURE_HWPSTATE, '!< Hardware P-state control */
  91.              CPU_FEATURE_CONSTANT_TSC, '!< TSC ticks at constant rate */
  92.              CPU_FEATURE_XOP, '!< The XOP instruction set (same as the old CPU_FEATURE_SSE5) */
  93.              CPU_FEATURE_FMA3, '!< The FMA3 instruction set */
  94.              CPU_FEATURE_FMA4, '!< The FMA4 instruction set */
  95.              CPU_FEATURE_TBM, '!< Trailing bit manipulation instruction support */
  96.              CPU_FEATURE_F16C, '!< 16-bit FP convert instruction support */
  97.              CPU_FEATURE_RDRAND, '!< RdRand instruction */
  98.              CPU_FEATURE_X2APIC, '!< x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) also see standard level 0000_000Bh */
  99.              CPU_FEATURE_CPB, '!< Core performance boost */
  100.              CPU_FEATURE_APERFMPERF, '!< MPERF/APERF MSRs support */
  101.              CPU_FEATURE_PFI, '!< Processor Feedback Interface support */
  102.              CPU_FEATURE_PA,        '!< Processor accumulator */
  103.              CPU_FEATURE_AVX2, '!< AVX2 instructions */
  104.              CPU_FEATURE_BMI1, '!< BMI1 instructions */
  105.              CPU_FEATURE_BMI2, '!< BMI2 instructions */
  106.              CPU_FEATURE_HLE, '!< Hardware Lock Elision prefixes */
  107.              CPU_FEATURE_RTM, '!< Restricted Transactional Memory instructions */
  108.              CPU_FEATURE_AVX512F, '!< AVX-512 Foundation */
  109.              CPU_FEATURE_AVX512DQ, '!< AVX-512 Double/Quad granular insns */
  110.              CPU_FEATURE_AVX512PF, '!< AVX-512 Prefetch */
  111.              CPU_FEATURE_AVX512ER, '!< AVX-512 Exponential/Reciprocal */
  112.              CPU_FEATURE_AVX512CD, '!< AVX-512 Conflict detection */
  113.              CPU_FEATURE_SHA_NI, '!< SHA-1/SHA-256 instructions */
  114.              CPU_FEATURE_AVX512BW, '!< AVX-512 Byte/Word granular insns */
  115.              CPU_FEATURE_AVX512VL, '!< AVX-512 128/256 vector length extensions */
  116.              CPU_FEATURE_SGX, '!< SGX extensions. Non-autoritative, check cpu_id_t::sgx::present to verify presence */
  117.              CPU_FEATURE_RDSEED, '!< RDSEED instruction */
  118.              CPU_FEATURE_ADX,
  119.              NUM_CPU_FEATURES
  120.  
  121. Private Enum VENDOR_INTEL = 0,  '/*!< Intel CPU */
  122.                VENDOR_AMD,        '/*!< AMD CPU */
  123.                VENDOR_CYRIX,      '/*!< Cyrix CPU */
  124.                VENDOR_NEXGEN,     '/*!< NexGen CPU */
  125.                VENDOR_TRANSMETA,  '/*!< Transmeta CPU */
  126.                VENDOR_UMC,        '/*!< x86 CPU by UMC */
  127.                VENDOR_CENTAUR,    '/*!< x86 CPU by IDT */
  128.                VENDOR_RISE,       '/*!< x86 CPU by Rise Technology */
  129.                VENDOR_SIS,        '/*!< x86 CPU by SiS */
  130.                VENDOR_NSC,        '/*!< x86 CPU by National Semiconductor */
  131.                NUM_CPU_VENDORS,   '/*!< Valid CPU vendor ids: 0..NUM_CPU_VENDORS - 1 */
  132.              VENDOR_UNKNOWN = -1
  133.  
  134. Public Struct cpu_list_t
  135.      num_entries As Integer
  136.      names As String
  137. End Struct
  138.  
  139. Public Struct cpu_raw_data_t
  140.   basic_cpuid[32, 4] As Integer
  141.   ext_cpuid[32, 4] As Integer
  142.   intel_fn4[8, 4] As Integer
  143.   intel_fn11[4, 4] As Integer
  144.   intel_fn12h[4, 4] As Integer
  145.   intel_fn14h[4, 4] As Integer
  146. End Struct
  147.  
  148. Public Struct cpu_sgx_t
  149.   present As Integer
  150.   max_enclave_32bit As Byte
  151.   max_enclave_64bit As Byte
  152.   flags[14] As Byte
  153.   num_epc_sections As Integer
  154.   misc_select As Integer
  155.   secs_attributes As Long
  156.   secs_xfrm As Long
  157. End Struct
  158.  
  159. Public Struct cpu_id_t
  160.   vendor_str[16] As Byte                   '       0 -  15
  161.   brand_str[64] As Byte                     '     16 -  79
  162.   vendor As Integer                            '     80 -  83
  163.   flags[124] As Byte                            '    84 - 211
  164.   family As Integer                              '  212 - 215
  165.   model As Integer                             '  216 - 219
  166.   stepping As Integer                         '  220 - 223
  167.   ext_family As Integer                      '  224 - 227
  168.   ext_model As Integer                     '  228 - 231
  169.   num_cores As Integer                    '  232 - 235
  170.   num_logical_cpus As Integer       '  236 - 239
  171.   total_logical_cpus As Integer       '  240 - 243
  172.   l1_data_cache As Integer             '  244 - 247
  173.   l1_instruction_cache As Integer  '  248 - 251
  174.   l2_cache As Integer                       '  252 - 255
  175.   l3_cache As Integer                       '  256 - 259
  176.   l4_cache As Integer                       '  260 - 263
  177.   l1_assoc As Integer                       '  264 - 267
  178.   l2_assoc As Integer                       '  268 - 271
  179.   l3_assoc As Integer                       '  272 - 275
  180.   l4_assoc As Integer                       '  276 - 279
  181.   l1_cacheline As Integer                '  280 - 283
  182.   l2_cacheline As Integer                '  284 - 287
  183.   l3_cacheline As Integer                '  288 - 291
  184.   l4_cacheline As Integer                '  292 - 295
  185.   cpu_codename[64] As Byte         '  296 - 359
  186.   sse_size As Integer                       '  360 - 363
  187.   detection_hints[16] As Byte         '  364 - 379
  188.   sgx As Struct Cpu_sgx_t              '  380 - 431
  189. End Struct
  190.  
  191. Public Struct cpu_mark_t
  192.   tsc As Long
  193.   sys_clock As Long
  194. End Struct
  195.  
  196. Public Struct cpu_epc_t
  197.   start_addr As Long
  198.     length As Long
  199. End Struct
  200.  
  201. ' int cpuid_present(void)
  202. ' Checks if the CPUID instruction is supported.
  203. Private Extern cpuid_present() As Integer
  204.  
  205. ' int cpuid_get_raw_data(struct cpu_raw_data_t* data)
  206. ' Obtains the raw CPUID data from the current CPU.
  207. Private Extern cpuid_get_raw_data(data As Cpu_raw_data_t) As Integer
  208.  
  209. '/ * *
  210. ' * @brief Returns the short textual representation Of a CPU flag
  211. ' * @param feature - the feature, whose textual representation Is Wanted.
  212. ' * @returns a constant string Like "fpu", "tsc", "sse2", etc.
  213. ' * @note the names Of the returned flags are compatible With those From
  214. ' * / proc / cpuinfo In Linux, With the exception Of `tm_amd'
  215. ' * /
  216. 'Const char * cpu_feature_str(cpu_feature_t feature);
  217. Private Extern cpu_feature_str(cpu_feature_t As Integer) As String
  218.  
  219. ' const char* cpuid_error(void)
  220. ' Returns textual description of the last error.
  221. Private Extern cpuid_error() As String
  222.  
  223. ' int cpu_identify(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
  224. ' Identifies the CPU.
  225. Private Extern cpu_identify(raw As Cpu_raw_data_t, data As Cpu_id_t) As Integer
  226.  
  227. ' void cpu_tsc_mark(struct cpu_mark_t* mark)
  228. ' Store TSC and timing info.
  229. Private Extern cpu_tsc_mark(mark As Cpu_mark_t)
  230.  
  231. ' void cpu_tsc_unmark(struct cpu_mark_t* mark)
  232. ' Calculate TSC and timing difference.
  233. Private Extern cpu_tsc_unmark(mark As Cpu_mark_t)
  234.  
  235. ' int cpu_clock(void)
  236. ' Get the CPU clock frequency (all-in-one method).
  237. Private Extern cpu_clock() As Integer
  238.  
  239. 'cpu_vendor_t cpuid_get_vendor(void);
  240. Private Extern cpuid_get_vendor() As Integer
  241.  
  242. 'void cpuid_get_cpu_list(cpu_vendor_t vendor, struct cpu_list_t* list);
  243. Private Extern cpuid_get_cpu_list(cpu_vendor_t As String, list As Cpu_list_t) As String
  244. ' int cpu_clock_by_os(void)
  245. ' Returns the CPU clock, as reported by the OS.
  246. Private Extern cpu_clock_by_os() As Integer
  247.  
  248. ' int cpu_clock_by_ic(int millis, int runs)
  249. ' Measure the CPU clock frequency using instruction-counting.
  250. Private Extern cpu_clock_by_ic(millis As Integer, runs As Integer) As Integer
  251.  
  252. ' int cpu_clock_measure(int millis, int quad_check)
  253. ' Measure the CPU clock frequency.
  254. Private Extern cpu_clock_measure(millis As Integer, quad_check As Integer) As Integer
  255.  
  256.  
  257. Public Sub Main()
  258.  
  259.   Dim raw As New Cpu_raw_data_t
  260.   Dim data As New Cpu_id_t
  261.   Dim mark As New Cpu_mark_t
  262.   Dim names As New Cpu_list_t
  263.   Dim au As String
  264.   Dim dataflags As Pointer
  265.   Dim i As Integer
  266.     If Not cpuid_present() Then Error.Raise("Sorry, your CPU doesn't support CPUID !")
  267.     dataflags = Alloc(SizeOf(gb.Byte), 432)
  268.     If cpuid_get_raw_data(raw) < 0 Then
  269.       Error.Raise("Sorry, cannot get the CPUID raw data.\nError: " & cpuid_error())
  270.     Endif
  271.     If cpu_identify(raw, data) < 0 Then
  272.       Error.Raise("Sorry, CPU identification failed.\nError: " & cpuid_error())
  273.     Endif
  274.     If cpu_identify(raw, dataflags) < 0 Then
  275.       Error.Raise("Sorry, CPU identification failed.\nError: " & cpuid_error())
  276.     Endif
  277.  
  278.     cpu_tsc_mark(mark)
  279.     cpu_tsc_unmark(mark)
  280.     ' For i = 0 To 127
  281.     '  Print i, data.flags[i]
  282.     ' Next
  283.     ' Print Str@(dataflags)
  284.     ' Print Byte@(dataflags + 85)
  285.     For i = 0 To 109
  286.      Print cpu_feature_str(i); IIf(Byte@(dataflags + (i + 84)), " Present", " Absent")
  287.     Next
  288.     ' Print cpu_feature_str(1); IIf(Byte@(dataflags + 85), " Present", " Absent")
  289.     ' Print cpu_feature_str(CPU_FEATURE_DE); IIf(data.flags[CPU_FEATURE_DE], " Present", " Absent")
  290.     ' Print cpu_feature_str(CPU_FEATURE_SSE4_1); IIf(data.flags[CPU_FEATURE_SSE4_1], " Present", " Absent")
  291.     ' Print cpu_feature_str(CPU_FEATURE_SSE4_2); IIf(data.flags[CPU_FEATURE_SSE4_2], " Present", " Absent")
  292.     ' Print cpu_feature_str(CPU_FEATURE_3DNOWPREFETCH); IIf(data.flags[CPU_FEATURE_3DNOWPREFETCH], " Present", " Absent")
  293.     ' Print cpu_feature_str(CPU_FEATURE_SSE5); IIf(data.flags[CPU_FEATURE_SSE5], " Present", " Absent")
  294.     ' Print cpu_feature_str(CPU_FEATURE_SSE); IIf(data.flags[CPU_FEATURE_SSE], " Present", " Absent")
  295.     ' Print cpu_feature_str(CPU_FEATURE_SSE2); IIf(data.flags[CPU_FEATURE_SSE2], " Present", " Absent")
  296.     Print "   \"VENDOR_STR\":         "; String@(data.vendor_str.data)
  297.     Print "   \"CPU_CODENAME\":       "; String@(data.cpu_codename.data)
  298.     Print "   \"BRAND_STR\":          "; String@(data.brand_str.data)
  299.     Print "   \"VENDOR\":             "; data.vendor
  300.     Print "   \"NUM_CORES\":          "; data.num_cores
  301.     Print "   \"NUM_LOGICAL_CPUS\":   "; data.num_logical_cpus
  302.     Print "   \"TOTAL_LOGICAL_CPUS\": "; data.total_logical_cpus
  303.     Print "   \"FAMILY\":             "; data.family
  304.     Print "   \"MODEL\":              "; data.model
  305.     Print "   \"STEPPING\":           "; data.stepping
  306.     Print "   \"EXT_FAMILY\":         "; data.ext_family
  307.     Print "   \"EXT_MODEL\":          "; data.ext_model
  308.     au = IIf(data.detection_hints[CPU_HINT_SSE_SIZE_AUTH], "(authoritative)", "(non-authoritative)")
  309.     Print "   \"SSE_SIZE\":           "; data.sse_size; " bit "; au
  310.     Print "   \"CPU_CLOCK\":          "; cpu_clock(); " Mhz"
  311.     Print "   \"CPU_CLOCK_BY_OS\":    "; cpu_clock_by_os(); " Mhz"
  312.     Print "   \"CPU_CLOCK_BY_IC\":    "; cpu_clock_by_ic(25, 16); " Mhz"
  313.     Print "   \"CPU_CLOCK_MEASURE\":  "; cpu_clock_measure(400, 1); " Mhz"
  314.     Print "   \"L1_DATA_CACHE\":      "; data.l1_data_cache; " KB"
  315.     Print "   \"L1_INSTRUCTION_CACHE\": "; data.l1_instruction_cache; " KB"
  316.     Print "   \"L1_CACHELINE\":       "; data.l1_cacheline; " bytes"
  317.     Print "   \"L1_ASSOC\":           "; data.l1_assoc; "-way"
  318.     Print "   \"L2_CACHE\":           "; data.l2_cache; " KB"
  319.     Print "   \"L2_ASSOC\":           "; data.l2_assoc; "-way"
  320.     Print "   \"L2_CACHELINE\":       "; data.l2_cacheline; " bytes"
  321.     Print "   \"L3_CACHE\":           "; data.l3_cache; " KB"
  322.     Print "   \"L3_ASSOC\":           "; data.l3_assoc; "-way"
  323.     Print "   \"L3_CACHELINE\":       "; data.l3_cacheline; " bytes"
  324.     Print "   \"L4_CACHE\":           "; data.l4_cache; " KB"
  325.     Print "   \"L4_ASSOC\":           "; data.l4_assoc; "-way"
  326.     Print "   \"L4_CACHELINE\":       "; data.l4_cacheline; " bytes"
  327.     Print "   \"MARK_TSC\":           "; mark.tsc
  328.     Print "   \"MARK_SYS_CLOCK\":     "; mark.sys_clock
  329.     Free(dataflags)
  330. End
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