command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmpuuwzpojv F1 %co* o:* %i F1 %d']
stderr   =======================================================================
Warning: Selection "F1" did not match any object.
exitcode =======================================================================
0
================================================================================


VS


command  =======================================================================
['/home/tnt/data/quicklogic/sf/./symbiflow-arch-defs/build/env/conda/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   ./symbiflow-arch-defs/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmp8e8oc23n c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================