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  1. /*
  2. ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
  3.  
  4. Licensed under the Apache License, Version 2.0 (the "License");
  5. you may not use this file except in compliance with the License.
  6. You may obtain a copy of the License at
  7.  
  8. http://www.apache.org/licenses/LICENSE-2.0
  9.  
  10. Unless required by applicable law or agreed to in writing, software
  11. distributed under the License is distributed on an "AS IS" BASIS,
  12. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13. See the License for the specific language governing permissions and
  14. limitations under the License.
  15. */
  16.  
  17. #ifndef MCUCONF_H
  18. #define MCUCONF_H
  19.  
  20. /*
  21. * STM32F7xx drivers configuration.
  22. * The following settings override the default settings present in
  23. * the various device driver implementation headers.
  24. * Note that the settings for each driver only have effect if the whole
  25. * driver is enabled in halconf.h.
  26. *
  27. * IRQ priorities:
  28. * 15...0 Lowest...Highest.
  29. *
  30. * DMA priorities:
  31. * 0...3 Lowest...Highest.
  32. */
  33.  
  34. #define STM32F7xx_MCUCONF
  35. #define STM32F765_MCUCONF
  36. #define STM32F767_MCUCONF
  37. #define STM32F777_MCUCONF
  38. #define STM32F769_MCUCONF
  39. #define STM32F779_MCUCONF
  40.  
  41. /*
  42. * HAL driver system settings.
  43. */
  44. #define STM32_NO_INIT FALSE
  45. #define STM32_PVD_ENABLE FALSE
  46. #define STM32_PLS STM32_PLS_LEV0
  47. #define STM32_BKPRAM_ENABLE FALSE
  48. #define STM32_HSI_ENABLED TRUE
  49. #define STM32_LSI_ENABLED FALSE
  50. #define STM32_HSE_ENABLED TRUE
  51. #define STM32_LSE_ENABLED TRUE
  52. #define STM32_CLOCK48_REQUIRED TRUE
  53. #define STM32_SW STM32_SW_PLL
  54. #define STM32_PLLSRC STM32_PLLSRC_HSE
  55. #define STM32_PLLM_VALUE 8
  56. #define STM32_PLLN_VALUE 432
  57. #define STM32_PLLP_VALUE 2
  58. #define STM32_PLLQ_VALUE 9
  59. #define STM32_HPRE STM32_HPRE_DIV1
  60. #define STM32_PPRE1 STM32_PPRE1_DIV4
  61. #define STM32_PPRE2 STM32_PPRE2_DIV2
  62. #define STM32_RTCSEL STM32_RTCSEL_LSE
  63. #define STM32_RTCPRE_VALUE 25
  64. #define STM32_MCO1SEL STM32_MCO1SEL_HSI
  65. #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
  66. #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
  67. #define STM32_MCO2PRE STM32_MCO2PRE_DIV4
  68. #define STM32_TIMPRE_ENABLE FALSE
  69. #define STM32_I2SSRC STM32_I2SSRC_OFF
  70. #define STM32_PLLI2SN_VALUE 192
  71. #define STM32_PLLI2SP_VALUE 4
  72. #define STM32_PLLI2SQ_VALUE 4
  73. #define STM32_PLLI2SR_VALUE 4
  74. #define STM32_PLLI2SDIVQ_VALUE 2
  75. #define STM32_PLLSAIN_VALUE 192
  76. #define STM32_PLLSAIP_VALUE 4
  77. #define STM32_PLLSAIQ_VALUE 4
  78. #define STM32_PLLSAIR_VALUE 4
  79. #define STM32_PLLSAIDIVQ_VALUE 2
  80. #define STM32_PLLSAIDIVR_VALUE 2
  81. #define STM32_SAI1SEL STM32_SAI1SEL_OFF
  82. #define STM32_SAI2SEL STM32_SAI2SEL_OFF
  83. #define STM32_LCDTFT_REQUIRED FALSE
  84. #define STM32_USART1SEL STM32_USART1SEL_PCLK2
  85. #define STM32_USART2SEL STM32_USART2SEL_PCLK1
  86. #define STM32_USART3SEL STM32_USART3SEL_PCLK1
  87. #define STM32_UART4SEL STM32_UART4SEL_PCLK1
  88. #define STM32_UART5SEL STM32_UART5SEL_PCLK1
  89. #define STM32_USART6SEL STM32_USART6SEL_PCLK2
  90. #define STM32_UART7SEL STM32_UART7SEL_PCLK1
  91. #define STM32_UART8SEL STM32_UART8SEL_PCLK1
  92. #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
  93. #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
  94. #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
  95. #define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
  96. #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
  97. #define STM32_CECSEL STM32_CECSEL_LSE
  98. #define STM32_CK48MSEL STM32_CK48MSEL_PLL
  99. #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
  100. #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK
  101. #define STM32_SRAM2_NOCACHE FALSE
  102.  
  103. /*
  104. * IRQ system settings.
  105. */
  106. #define STM32_IRQ_EXTI0_PRIORITY 6
  107. #define STM32_IRQ_EXTI1_PRIORITY 6
  108. #define STM32_IRQ_EXTI2_PRIORITY 6
  109. #define STM32_IRQ_EXTI3_PRIORITY 6
  110. #define STM32_IRQ_EXTI4_PRIORITY 6
  111. #define STM32_IRQ_EXTI5_9_PRIORITY 6
  112. #define STM32_IRQ_EXTI10_15_PRIORITY 6
  113. #define STM32_IRQ_EXTI16_PRIORITY 6
  114. #define STM32_IRQ_EXTI17_PRIORITY 6
  115. #define STM32_IRQ_EXTI18_PRIORITY 6
  116. #define STM32_IRQ_EXTI19_PRIORITY 6
  117. #define STM32_IRQ_EXTI20_PRIORITY 6
  118. #define STM32_IRQ_EXTI21_PRIORITY 6
  119. #define STM32_IRQ_EXTI22_PRIORITY 6
  120. #define STM32_IRQ_EXTI23_PRIORITY 6
  121.  
  122. #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
  123. #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
  124. #define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
  125. #define STM32_IRQ_TIM1_CC_PRIORITY 7
  126. #define STM32_IRQ_TIM2_PRIORITY 7
  127. #define STM32_IRQ_TIM3_PRIORITY 7
  128. #define STM32_IRQ_TIM4_PRIORITY 7
  129. #define STM32_IRQ_TIM5_PRIORITY 7
  130. #define STM32_IRQ_TIM6_PRIORITY 7
  131. #define STM32_IRQ_TIM7_PRIORITY 7
  132. #define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
  133. #define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
  134. #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
  135. #define STM32_IRQ_TIM8_CC_PRIORITY 7
  136.  
  137. #define STM32_IRQ_USART1_PRIORITY 12
  138. #define STM32_IRQ_USART2_PRIORITY 12
  139. #define STM32_IRQ_USART3_PRIORITY 12
  140. #define STM32_IRQ_UART4_PRIORITY 12
  141. #define STM32_IRQ_UART5_PRIORITY 12
  142. #define STM32_IRQ_USART6_PRIORITY 12
  143. #define STM32_IRQ_UART7_PRIORITY 12
  144. #define STM32_IRQ_UART8_PRIORITY 12
  145.  
  146. /*
  147. * ADC driver system settings.
  148. */
  149. #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
  150. #define STM32_ADC_USE_ADC1 FALSE
  151. #define STM32_ADC_USE_ADC2 FALSE
  152. #define STM32_ADC_USE_ADC3 FALSE
  153. #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
  154. #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  155. #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
  156. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  157. #define STM32_ADC_ADC2_DMA_PRIORITY 2
  158. #define STM32_ADC_ADC3_DMA_PRIORITY 2
  159. #define STM32_ADC_IRQ_PRIORITY 6
  160. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
  161. #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
  162. #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
  163.  
  164. /*
  165. * CAN driver system settings.
  166. */
  167. #define STM32_CAN_USE_CAN1 FALSE
  168. #define STM32_CAN_USE_CAN2 FALSE
  169. #define STM32_CAN_USE_CAN3 FALSE
  170. #define STM32_CAN_CAN1_IRQ_PRIORITY 11
  171. #define STM32_CAN_CAN2_IRQ_PRIORITY 11
  172. #define STM32_CAN_CAN3_IRQ_PRIORITY 11
  173.  
  174. /*
  175. * DAC driver system settings.
  176. */
  177. #define STM32_DAC_DUAL_MODE FALSE
  178. #define STM32_DAC_USE_DAC1_CH1 FALSE
  179. #define STM32_DAC_USE_DAC1_CH2 FALSE
  180. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
  181. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
  182. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
  183. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
  184. #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  185. #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  186.  
  187. /*
  188. * GPT driver system settings.
  189. */
  190. #define STM32_GPT_USE_TIM1 FALSE
  191. #define STM32_GPT_USE_TIM2 FALSE
  192. #define STM32_GPT_USE_TIM3 FALSE
  193. #define STM32_GPT_USE_TIM4 FALSE
  194. #define STM32_GPT_USE_TIM5 FALSE
  195. #define STM32_GPT_USE_TIM6 FALSE
  196. #define STM32_GPT_USE_TIM7 FALSE
  197. #define STM32_GPT_USE_TIM8 FALSE
  198. #define STM32_GPT_USE_TIM9 FALSE
  199. #define STM32_GPT_USE_TIM10 FALSE
  200. #define STM32_GPT_USE_TIM11 FALSE
  201. #define STM32_GPT_USE_TIM12 FALSE
  202. #define STM32_GPT_USE_TIM13 FALSE
  203. #define STM32_GPT_USE_TIM14 FALSE
  204. #define STM32_GPT_USE_TIM15 FALSE
  205. #define STM32_GPT_USE_TIM16 FALSE
  206. #define STM32_GPT_USE_TIM17 FALSE
  207.  
  208. /*
  209. * I2C driver system settings.
  210. */
  211. #define STM32_I2C_USE_I2C1 FALSE
  212. #define STM32_I2C_USE_I2C2 FALSE
  213. #define STM32_I2C_USE_I2C3 FALSE
  214. #define STM32_I2C_USE_I2C4 TRUE
  215. #define STM32_I2C_BUSY_TIMEOUT 50
  216. #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  217. #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  218. #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  219. #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  220. #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  221. #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  222. #define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  223. #define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  224. #define STM32_I2C_I2C1_IRQ_PRIORITY 5
  225. #define STM32_I2C_I2C2_IRQ_PRIORITY 5
  226. #define STM32_I2C_I2C3_IRQ_PRIORITY 5
  227. #define STM32_I2C_I2C4_IRQ_PRIORITY 5
  228. #define STM32_I2C_I2C1_DMA_PRIORITY 3
  229. #define STM32_I2C_I2C2_DMA_PRIORITY 3
  230. #define STM32_I2C_I2C3_DMA_PRIORITY 3
  231. #define STM32_I2C_I2C4_DMA_PRIORITY 3
  232. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  233.  
  234. /*
  235. * ICU driver system settings.
  236. */
  237. #define STM32_ICU_USE_TIM1 FALSE
  238. #define STM32_ICU_USE_TIM2 FALSE
  239. #define STM32_ICU_USE_TIM3 FALSE
  240. #define STM32_ICU_USE_TIM4 FALSE
  241. #define STM32_ICU_USE_TIM5 FALSE
  242. #define STM32_ICU_USE_TIM8 FALSE
  243. #define STM32_ICU_USE_TIM9 FALSE
  244. #define STM32_ICU_USE_TIM10 FALSE
  245. #define STM32_ICU_USE_TIM11 FALSE
  246. #define STM32_ICU_USE_TIM12 FALSE
  247. #define STM32_ICU_USE_TIM13 FALSE
  248. #define STM32_ICU_USE_TIM14 FALSE
  249. #define STM32_ICU_USE_TIM15 FALSE
  250. #define STM32_ICU_USE_TIM16 FALSE
  251. #define STM32_ICU_USE_TIM17 FALSE
  252.  
  253. /*
  254. * MAC driver system settings.
  255. */
  256. #define STM32_MAC_TRANSMIT_BUFFERS 2
  257. #define STM32_MAC_RECEIVE_BUFFERS 4
  258. #define STM32_MAC_BUFFERS_SIZE 1522
  259. #define STM32_MAC_PHY_TIMEOUT 100
  260. #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
  261. #define STM32_MAC_ETH1_IRQ_PRIORITY 13
  262. #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
  263.  
  264. /*
  265. * PWM driver system settings.
  266. */
  267. #define STM32_PWM_USE_ADVANCED FALSE
  268. #define STM32_PWM_USE_TIM1 TRUE
  269. #define STM32_PWM_USE_TIM2 FALSE
  270. #define STM32_PWM_USE_TIM3 TRUE
  271. #define STM32_PWM_USE_TIM4 FALSE
  272. #define STM32_PWM_USE_TIM5 FALSE
  273. #define STM32_PWM_USE_TIM8 FALSE
  274. #define STM32_PWM_USE_TIM9 FALSE
  275. #define STM32_PWM_USE_TIM10 FALSE
  276. #define STM32_PWM_USE_TIM11 FALSE
  277. #define STM32_PWM_USE_TIM12 FALSE
  278. #define STM32_PWM_USE_TIM13 FALSE
  279. #define STM32_PWM_USE_TIM14 FALSE
  280. #define STM32_PWM_USE_TIM15 FALSE
  281. #define STM32_PWM_USE_TIM16 FALSE
  282. #define STM32_PWM_USE_TIM17 FALSE
  283.  
  284. /*
  285. * RTC driver system settings.
  286. */
  287. #define STM32_RTC_PRESA_VALUE 32
  288. #define STM32_RTC_PRESS_VALUE 1024
  289. #define STM32_RTC_CR_INIT 0
  290. #define STM32_RTC_TAMPCR_INIT 0
  291.  
  292. /*
  293. * SDC driver system settings.
  294. */
  295. #define STM32_SDC_USE_SDMMC1 FALSE
  296. #define STM32_SDC_USE_SDMMC2 FALSE
  297. #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
  298. #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
  299. #define STM32_SDC_SDMMC_READ_TIMEOUT 1000
  300. #define STM32_SDC_SDMMC_CLOCK_DELAY 10
  301. #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  302. #define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
  303. #define STM32_SDC_SDMMC1_DMA_PRIORITY 3
  304. #define STM32_SDC_SDMMC2_DMA_PRIORITY 3
  305. #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
  306. #define STM32_SDC_SDMMC2_IRQ_PRIORITY 9
  307.  
  308. /*
  309. * SERIAL driver system settings.
  310. */
  311. #define STM32_SERIAL_USE_USART1 FALSE
  312. #define STM32_SERIAL_USE_USART2 FALSE
  313. #define STM32_SERIAL_USE_USART3 TRUE
  314. #define STM32_SERIAL_USE_UART4 FALSE
  315. #define STM32_SERIAL_USE_UART5 FALSE
  316. #define STM32_SERIAL_USE_USART6 FALSE
  317. #define STM32_SERIAL_USE_UART7 FALSE
  318. #define STM32_SERIAL_USE_UART8 FALSE
  319.  
  320. /*
  321. * SIO driver system settings.
  322. */
  323. #define STM32_SIO_USE_USART1 FALSE
  324. #define STM32_SIO_USE_USART2 FALSE
  325. #define STM32_SIO_USE_USART3 FALSE
  326. #define STM32_SIO_USE_UART4 FALSE
  327. #define STM32_SIO_USE_UART5 FALSE
  328. #define STM32_SIO_USE_USART6 FALSE
  329. #define STM32_SIO_USE_UART7 FALSE
  330. #define STM32_SIO_USE_UART8 FALSE
  331.  
  332. /*
  333. * SPI driver system settings.
  334. */
  335. #define STM32_SPI_USE_SPI1 FALSE
  336. #define STM32_SPI_USE_SPI2 TRUE
  337. #define STM32_SPI_USE_SPI3 FALSE
  338. #define STM32_SPI_USE_SPI4 TRUE
  339. #define STM32_SPI_USE_SPI5 FALSE
  340. #define STM32_SPI_USE_SPI6 FALSE
  341. #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
  342. #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  343. #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  344. #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  345. #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  346. #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  347. #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
  348. #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
  349. #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  350. #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
  351. #define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
  352. #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
  353. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  354. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  355. #define STM32_SPI_SPI3_DMA_PRIORITY 1
  356. #define STM32_SPI_SPI4_DMA_PRIORITY 1
  357. #define STM32_SPI_SPI5_DMA_PRIORITY 1
  358. #define STM32_SPI_SPI6_DMA_PRIORITY 1
  359. #define STM32_SPI_SPI1_IRQ_PRIORITY 10
  360. #define STM32_SPI_SPI2_IRQ_PRIORITY 10
  361. #define STM32_SPI_SPI3_IRQ_PRIORITY 10
  362. #define STM32_SPI_SPI4_IRQ_PRIORITY 10
  363. #define STM32_SPI_SPI5_IRQ_PRIORITY 10
  364. #define STM32_SPI_SPI6_IRQ_PRIORITY 10
  365. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  366.  
  367. /*
  368. * ST driver system settings.
  369. */
  370. #define STM32_ST_IRQ_PRIORITY 8
  371. #define STM32_ST_USE_TIMER 2
  372.  
  373. /*
  374. * TRNG driver system settings.
  375. */
  376. #define STM32_TRNG_USE_RNG1 FALSE
  377.  
  378. /*
  379. * UART driver system settings.
  380. */
  381. #define STM32_UART_USE_USART1 FALSE
  382. #define STM32_UART_USE_USART2 FALSE
  383. #define STM32_UART_USE_USART3 TRUE
  384. #define STM32_UART_USE_UART4 FALSE
  385. #define STM32_UART_USE_UART5 FALSE
  386. #define STM32_UART_USE_USART6 FALSE
  387. #define STM32_UART_USE_UART7 FALSE
  388. #define STM32_UART_USE_UART8 FALSE
  389. #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
  390. #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  391. #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  392. #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  393. #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
  394. #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  395. #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  396. #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  397. #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  398. #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  399. #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  400. #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  401. #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  402. #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
  403. #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  404. #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  405. #define STM32_UART_USART1_DMA_PRIORITY 0
  406. #define STM32_UART_USART2_DMA_PRIORITY 0
  407. #define STM32_UART_USART3_DMA_PRIORITY 0
  408. #define STM32_UART_UART4_DMA_PRIORITY 0
  409. #define STM32_UART_UART5_DMA_PRIORITY 0
  410. #define STM32_UART_USART6_DMA_PRIORITY 0
  411. #define STM32_UART_UART7_DMA_PRIORITY 0
  412. #define STM32_UART_UART8_DMA_PRIORITY 0
  413. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  414.  
  415. /*
  416. * USB driver system settings.
  417. */
  418. #define STM32_USB_USE_OTG1 TRUE
  419. #define STM32_USB_USE_OTG2 FALSE
  420. #define STM32_USB_OTG1_IRQ_PRIORITY 14
  421. #define STM32_USB_OTG2_IRQ_PRIORITY 14
  422. #define STM32_USB_OTG1_RX_FIFO_SIZE 512
  423. #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
  424.  
  425. /*
  426. * WDG driver system settings.
  427. */
  428. #define STM32_WDG_USE_IWDG FALSE
  429.  
  430. /*
  431. * WSPI driver system settings.
  432. */
  433. #define STM32_WSPI_USE_QUADSPI1 TRUE
  434. #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  435. #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 255
  436.  
  437. #endif /* MCUCONF_H */
  438.  
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