`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    17:26:08 05/10/2012
// Design Name:
// Module Name:    Calc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Proc(
	input clk,
	input [7:0] iDue,
	output [7:0] oBalance
);

	reg [7:0] balance = 0;

	initial
		begin


			balance = balance + 1;

			assign oBalance = balance;

			$finish;
		end
endmodule