library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity top is
	PORT(
		clk50, reset50 : in STD_LOGIC;
		hsyncG, vsyncG : out STD_LOGIC;
		red, green, blue : out STD_LOGIC_VECTOR(3 downto 0)
		);
end top;


architecture vhdl of top is

--Integration du fichier digit


component HEX32 is
	Port (  val : in  STD_LOGIC_VECTOR (31 downto 0);
           posX : in  STD_LOGIC_VECTOR (9 downto 0):= "0001100100";
           posY : in  STD_LOGIC_VECTOR (9 downto 0):= "0001100100";
           beamX : in  STD_LOGIC_VECTOR (9 downto 0);
           beamY : in  STD_LOGIC_VECTOR (9 downto 0);
			  beamValid : in std_logic;
           red : in  STD_LOGIC_VECTOR (3 downto 0):="0001";
           green : in  STD_LOGIC_VECTOR (3 downto 0):="1111";
           blue : in  STD_LOGIC_VECTOR (3 downto 0):="0001";
           redOut : out  STD_LOGIC_VECTOR (3 downto 0);
           greenOut : out  STD_LOGIC_VECTOR (3 downto 0);
           blueOut : out  STD_LOGIC_VECTOR (3 downto 0) );
end component;

--Integration du fichier controlVGA

component controlVGA is
	Port(
	 clk : in std_logic;
    reset : in std_logic;
    rIn, gIn, bIn : in std_logic_vector(3 downto 0);
    rOut, gOut, bOut : out std_logic_vector(3 downto 0);
	 beamX, beamY : out std_logic_vector(9 downto 0);
	 beamValid : out std_logic;
    blank : inout std_logic;
    vsync : out std_logic;
    hsync : out std_logic
    );
end component;


component cpt is
Port(
	clk,reset: in std_logic;
	compteur : out std_logic_vector(31 downto 0)
	);
end component;


--création des signaux (donc toutes chemins à rélier)

signal rSig, gSig, bSig: STD_LOGIC_VECTOR(3 downto 0);   --entrée D
signal beamXSig, beamYSig: STD_LOGIC_VECTOR(9 downto 0); --entrée D
signal beamValidSig : std_logic;   --entrée D
signal posXSig, posYSig : STD_LOGIC_VECTOR (9 downto 0);   --entrée D

signal redOutSig,greenOutSig, blueOutSig : STD_LOGIC_VECTOR (3 downto 0); --sortie D

signal comptSig : STD_LOGIC_VECTOR (31 downto 0);--compteur SIGNAL
signal timerSig: std_logic_vector(25 downto 0); --2^26 > 50 000 000

begin
	timerSig <= "00000000000000000000000000" when reset50 ='1'
					else "00000000000000000000000000" when timerSig = "10111110101111000010000000" AND rising_edge(clk50)
					else std_logic_vector(unsigned(timerSig) + 1) when rising_edge(clk50);

	comptSig <= std_logic_vector(unsigned(comptSig) + 1) when timerSig="10111110101111000010000000"
					else "00000000000000000000000000000000" when reset50 ='1'
					else "00000000000000000000000000000000" when comptSig = "11111111111111111111111111111111";

idigit : HEX32 port map (

	val => comptSig,

	redOut => redOutSig,
	greenOut => greenOutSig,
	blueOut => blueOutSig,

	beamX => beamXSig,
	beamY => beamYSig,
	beamValid => beamValidSig

);

--iCpt : cpt port map (

		--reset => reset50,
	--clk => clk50,
	--compteur => comptSig

--);

-- transfert entre les composants et l'exterieur
iVGA : controlVGA port map(

	rIn => redOutSig,
	gIn => greenOutSig,
	bIn => blueOutSig,

	hsync => hsyncG,
	vsync => vsyncG,

	beamX => beamXSig,
	beamY => beamYSig,
	beamValid => beamValidSig,

	clk => clk50,
	reset => reset50,

	rOut => rSig,
	gOut => gSig,
	bOut => bSig
);

red <= rSig;
green <= gSig;
blue <= bSig;

end vhdl;





--cpt_r <= (others => '0') when reset50='1'
  --       else cpt_c when rising_edge(clk50);

--cpt_c <= (others => '0') when cpt_r="10111110101111000010000000" else
	--		std_logic_vector(unsigned(cpt_r)+1);

--comptSig_c <= std_logic_vector(unsigned(comptSig_r) + 1)
	--				when cpt_r="10111110101111000010000000" else
		--			comptSig_r;

--comptSig_r <= (others => '0') when reset50='1'
	--				else comptSig_c when rising_edge(clk50);