RCC->CR |= RCC_CR_HSEON;
	while (!(RCC->CR & RCC_CR_HSERDY)){};

	FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY;

	RCC->CFGR &= ~RCC_CFGR_SW; //clear SW bits
	RCC->CFGR |= RCC_CFGR_SW_0; //SYSCLK is HSE
	while (!(RCC->CFGR & RCC_CFGR_SWS_0)){};

		RCC->CR &= ~RCC_CR_PLLON;   //PLL OFF

	RCC->CFGR &= ~RCC_CFGR_HPRE; //AHB = 1;
	RCC->CFGR &= ~RCC_CFGR_PPRE2;
	RCC->CFGR &= ~RCC_CFGR_PPRE1;
	RCC->CFGR |= RCC_CFGR_PPRE2_2; //APB2 = 2;
	RCC->CFGR |= RCC_CFGR_PPRE1_0 | RCC_CFGR_PPRE1_2; // APB1 = 4;

	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM;
  RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLN;
  RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLQ;
	RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_3; //PLLM = 12
	RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_8; //PLLN = 336;
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLP; // PLLP = 2;
	RCC->PLLCFGR |= RCC_PLLCFGR_PLLQ_2; //PLLQ = 4;

	RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
	RCC->CR |= RCC_CR_PLLON;
	while (!(RCC->CR & RCC_CR_PLLON)){};


	RCC->CFGR &= ~RCC_CFGR_SW; //clear SW bits
	RCC->CFGR |= RCC_CFGR_SW_1; //SYSCLK is PLL
	while (!(RCC->CFGR & RCC_CFGR_SWS_1)){};