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ex5.s

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Dec 13th, 2017
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ARM 0.82 KB | None | 0 0
  1. .include "configuration.inc"
  2. .include "inter.inc"
  3.  
  4. mov r0, #0
  5. ADDEXC 0x18, irq_handler
  6. ADDEXC 0x1C, fiq_handler
  7.  
  8. main:
  9.  
  10.     mov r0, #0b11010010
  11.     msr cpsr_c, r0
  12.     mov sp, #0x8000
  13.    
  14.     mov r0, #0b11010001
  15.     msr cpsr_c, r0
  16.     mov sp, #0x4000
  17.    
  18.     mov r0, #0b11010011
  19.     msr cpsr_c, r0
  20.     mov sp, #0x8000000
  21.    
  22.    
  23.     ldr r0, =STBASE
  24.     ldr r1, [r0, #STCLO]
  25.     add r1, #4000
  26.     str r1, [r0, #STC1]
  27.    
  28.     ldr r0, =INTBASE
  29.     ldr r2, =0b0010
  30.     str r2, [r0, #INTENIRQ1]
  31.    
  32.     mov r1, #0b01010011
  33.     msr cpsr_c, r1
  34.    
  35.     ldr r3, =0
  36.     ldr r4, =0x010
  37.    
  38. end:    b end
  39.  
  40. fiq_handler:
  41.    
  42. irq_handler:
  43.     ldr r0, =GPBASE
  44.     eors r3, r3, #0b01
  45.     streq r4, [r0, #GPSET0]
  46.     strne r4, [r0, #GPCLR0]
  47.    
  48.    
  49.     ldr r0, =STBASE
  50.     mov r1, #0b0010
  51.     str r1, [r0, #STCS]
  52.    
  53.     ldr r0, =STBASE
  54.     ldr r1, [r0, #STCLO]
  55.     add r1, #4000
  56.     str r1, [r0, #STC1]
  57.    
  58.     subs pc, lr, #4
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