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  1. /*
  2. * Copyright 2018 NXP
  3. * Copyright 2019 Variscite Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15.  
  16. /dts-v1/;
  17.  
  18. #include "fsl-imx8mm.dtsi"
  19.  
  20. / {
  21. model = "Variscite DART-MX8MM board";
  22. compatible = "variscite,dart-mx8mm", "fsl,imx8mm";
  23.  
  24. chosen {
  25. bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
  26. stdout-path = &uart1;
  27. };
  28.  
  29. regulators {
  30. compatible = "simple-bus";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33.  
  34. reg_usdhc2_vmmc: regulator-usdhc2 {
  35. compatible = "regulator-fixed";
  36. regulator-name = "VSD_3V3";
  37. regulator-min-microvolt = <3300000>;
  38. regulator-max-microvolt = <3300000>;
  39. gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  40. off-on-delay = <20000>;
  41. enable-active-high;
  42. };
  43.  
  44. reg_eth_phy: regulator-eth-phy {
  45. compatible = "regulator-fixed";
  46. regulator-name = "eth_phy_pwr";
  47. regulator-min-microvolt = <3300000>;
  48. regulator-max-microvolt = <3300000>;
  49. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  50. };
  51.  
  52. reg_wifi_en: wifi_en {
  53. compatible = "regulator-fixed";
  54. regulator-name = "WIFI_REG_ON";
  55. regulator-min-microvolt = <3300000>;
  56. regulator-max-microvolt = <3300000>;
  57. };
  58.  
  59. reg_audio: audio_vdd {
  60. compatible = "regulator-fixed";
  61. regulator-name = "wm8904_supply";
  62. regulator-min-microvolt = <3300000>;
  63. regulator-max-microvolt = <3300000>;
  64. regulator-always-on;
  65. };
  66. };
  67.  
  68. can0_osc: can0_osc {
  69. compatible = "fixed-clock";
  70. #clock-cells = <0>;
  71. clock-frequency = <20000000>;
  72. };
  73.  
  74. reserved-memory {
  75. /* cma region is provided by kernel command line as cma=<size>MB */
  76. /delete-node/ linux,cma;
  77. };
  78.  
  79. sound-spdif {
  80. compatible = "fsl,imx-audio-spdif";
  81. model = "imx-spdif";
  82. spdif-controller = <&spdif1>;
  83. spdif-out;
  84. spdif-in;
  85. status = "disabled";
  86. };
  87.  
  88. sound-micfil {
  89. compatible = "fsl,imx-audio-micfil";
  90. model = "imx-audio-micfil";
  91. cpu-dai = <&micfil>;
  92. status = "disabled";
  93. };
  94.  
  95. sound-wm8904 {
  96. compatible = "fsl,imx-audio-wm8904";
  97. model = "imx-wm8904";
  98. audio-cpu = <&sai3>;
  99. audio-codec = <&wm8904>;
  100. audio-routing =
  101. "Headphone Jack", "HPOUTL",
  102. "Headphone Jack", "HPOUTR",
  103. "IN2L", "Line In Jack",
  104. "IN2R", "Line In Jack",
  105. "IN1L", "Mic Jack",
  106. "Playback", "CPU-Playback",
  107. "CPU-Capture", "Capture";
  108. status = "okay";
  109. };
  110.  
  111. // https://www.kernel.org/doc/Documentation/devicetree/bindings/sound/simple-card.txt
  112.  
  113. sound {
  114. compatible = "simple-audio-card";
  115. simple-audio-card,name = "CS4344";
  116. simple-audio-card,format = "i2s";
  117. simple-audio-card,widgets =
  118. "Line", "Line Out";
  119. simple-audio-card,routing =
  120. "Line Out", "LLOUT",
  121. "Line Out", "RLOUT";
  122. simple-audio-card,cpu {
  123. sound-dai = <&sai5>;
  124. };
  125. simple-audio-card,codec {
  126. sound-dai = <&codec1>;
  127. };
  128. };
  129.  
  130. codec1: codec1 {
  131. compatible = "linux,snd-soc-dummy";
  132. #sound-dai-cells = <0>;
  133. status = "okay";
  134. };
  135.  
  136.  
  137. gpio-keys {
  138. compatible = "gpio-keys";
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&pinctrl_gpio_keys>;
  141.  
  142. up {
  143. label = "Up";
  144. gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  145. linux,code = <KEY_UP>;
  146. };
  147.  
  148. down {
  149. label = "Down";
  150. gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
  151. linux,code = <KEY_DOWN>;
  152. };
  153.  
  154. };
  155.  
  156. leds {
  157. compatible = "gpio-leds";
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&pinctrl_leds>;
  160.  
  161. emmc {
  162. label = "eMMC";
  163. gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
  164. linux,default-trigger = "mmc2";
  165. };
  166. };
  167.  
  168. };
  169.  
  170. &clk {
  171. assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>;
  172. assigned-clock-rates = <786432000>;
  173. };
  174.  
  175. &iomuxc {
  176. pinctrl-names = "default";
  177.  
  178. imx8mm-var-dart {
  179.  
  180. pinctrl_csi1: csi1grp {
  181. fsl,pins = <
  182. MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
  183. MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x19
  184. >;
  185. };
  186.  
  187. pinctrl_fec1: fec1grp {
  188. fsl,pins = <
  189. MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  190. MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  191. MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  192. MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  193. MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  194. MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  195. MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  196. MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  197. MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  198. MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  199. MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  200. MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  201. MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  202. MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  203. MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
  204. MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
  205. >;
  206. };
  207.  
  208. pinctrl_flexspi0: flexspi0grp {
  209. fsl,pins = <
  210. MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
  211. MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
  212. MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
  213. MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
  214. MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
  215. MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
  216. >;
  217. };
  218.  
  219. pinctrl_i2c1: i2c1grp {
  220. fsl,pins = <
  221. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  222. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  223. >;
  224. };
  225.  
  226. pinctrl_i2c2: i2c2grp {
  227. fsl,pins = <
  228. MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  229. MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  230. >;
  231. };
  232.  
  233. pinctrl_i2c3: i2c3grp {
  234. fsl,pins = <
  235. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  236. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  237. >;
  238. };
  239.  
  240. pinctrl_i2c4: i2c4grp {
  241. fsl,pins = <
  242. MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
  243. MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
  244. >;
  245. };
  246.  
  247. pinctrl_pcie0: pcie0grp {
  248. fsl,pins = <
  249. MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x41
  250. >;
  251. };
  252.  
  253. pinctrl_pmic: pmicirq {
  254. fsl,pins = <
  255. MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x41
  256. >;
  257. };
  258.  
  259. pinctrl_sai3: sai3grp {
  260. fsl,pins = <
  261. MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6
  262. MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6
  263. MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
  264. MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
  265. MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
  266. MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
  267. MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
  268. >;
  269. };
  270.  
  271. pinctrl_sai5: sai5grp {
  272. fsl,pins = <
  273. MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0xd6
  274. MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0xd6
  275. MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
  276. MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0xd6
  277. MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0xd6
  278. >;
  279. };
  280.  
  281. pinctrl_pdm: pdmgrp {
  282. fsl,pins = <
  283. MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
  284. MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
  285. MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
  286. MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
  287. MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
  288. MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
  289. MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
  290. >;
  291. };
  292.  
  293. pinctrl_spdif1: spdif1grp {
  294. fsl,pins = <
  295. MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
  296. MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
  297. >;
  298. };
  299.  
  300. pinctrl_uart1: uart1grp {
  301. fsl,pins = <
  302. MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
  303. MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
  304. >;
  305. };
  306.  
  307. pinctrl_uart2: uart2grp {
  308. fsl,pins = <
  309. MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
  310. MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
  311. >;
  312. };
  313.  
  314. pinctrl_uart3: uart3grp {
  315. fsl,pins = <
  316. MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
  317. MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
  318. >;
  319. };
  320.  
  321. pinctrl_uart4: uart4grp {
  322. fsl,pins = <
  323. MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
  324. MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
  325. MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
  326. MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
  327. >;
  328. };
  329.  
  330. pinctrl_usdhc1: usdhc1grp {
  331. fsl,pins = <
  332. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
  333. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
  334. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
  335. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
  336. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
  337. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
  338. >;
  339. };
  340.  
  341. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  342. fsl,pins = <
  343. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
  344. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
  345. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
  346. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
  347. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
  348. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
  349. >;
  350. };
  351.  
  352. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  353. fsl,pins = <
  354. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
  355. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
  356. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
  357. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
  358. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
  359. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
  360. >;
  361. };
  362.  
  363. pinctrl_usdhc2_gpio: usdhc2grpgpio {
  364. fsl,pins = <
  365. MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1
  366. MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
  367. >;
  368. };
  369.  
  370. pinctrl_usdhc2: usdhc2grp {
  371. fsl,pins = <
  372. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  373. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  374. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  375. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  376. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  377. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  378. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  379. >;
  380. };
  381.  
  382. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  383. fsl,pins = <
  384. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  385. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  386. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  387. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  388. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  389. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  390. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  391. >;
  392. };
  393.  
  394. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  395. fsl,pins = <
  396. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  397. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  398. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  399. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  400. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  401. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  402. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  403. >;
  404. };
  405.  
  406. pinctrl_usdhc3: usdhc3grp {
  407. fsl,pins = <
  408. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
  409. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  410. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  411. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  412. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  413. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  414. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  415. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  416. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  417. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  418. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  419. >;
  420. };
  421.  
  422. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  423. fsl,pins = <
  424. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
  425. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  426. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  427. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  428. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  429. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  430. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  431. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  432. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  433. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  434. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  435. >;
  436. };
  437.  
  438. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  439. fsl,pins = <
  440. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
  441. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  442. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  443. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  444. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  445. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  446. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  447. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  448. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  449. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  450. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  451. >;
  452. };
  453.  
  454. pinctrl_wdog: wdoggrp {
  455. fsl,pins = <
  456. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  457. >;
  458. };
  459.  
  460. pinctrl_wifi: wifigrp {
  461. fsl,pins = <
  462. MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0xc1 /* WIFI_3V3_PWR_EN */
  463. MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 /* WIFI_1V8_PWR_EN */
  464. MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 /* WIFI_REG_ON */
  465. MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 /* BT_REG_ON */
  466. MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1 /* BT_BUF_EN */
  467. >;
  468. };
  469.  
  470. pinctrl_typec: typecgrp {
  471. fsl,pins = <
  472. MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
  473. >;
  474. };
  475.  
  476. pinctrl_rtc: rtcgrp {
  477. fsl,pins = <
  478. MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1
  479. >;
  480. };
  481.  
  482. pinctrl_lvds: lvdsgrp {
  483. fsl,pins = <
  484. MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
  485. >;
  486. };
  487.  
  488. /*pinctrl_pwm1: pwm1grp {
  489. fsl,pins = <
  490. MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
  491. >;
  492. };*/
  493.  
  494. pinctrl_captouch: captouchgrp {
  495. fsl,pins = <
  496. MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x16
  497. MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
  498. >;
  499. };
  500.  
  501. pinctrl_ecspi1: ecspi1grp {
  502. fsl,pins = <
  503. MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
  504. MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
  505. MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
  506. MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
  507. MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13
  508. >;
  509. };
  510.  
  511. pinctrl_can: cangrp {
  512. fsl,pins = <
  513. MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
  514. >;
  515. };
  516.  
  517. pinctrl_restouch: restouchgrp {
  518. fsl,pins = <
  519. MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
  520. >;
  521. };
  522.  
  523. pinctrl_gpio_keys: keygrp {
  524. fsl,pins = <
  525. /*MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c6*/
  526. MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6
  527. /*MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c6*/
  528. MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x1c6
  529. >;
  530. };
  531.  
  532. pinctrl_leds: ledgrp {
  533. fsl,pins = <
  534. MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c6
  535. MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c6
  536. MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c6
  537. MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1c6
  538. >;
  539. };
  540. };
  541. };
  542.  
  543. &i2c1 {
  544. clock-frequency = <100000>;
  545. pinctrl-names = "default";
  546. pinctrl-0 = <&pinctrl_i2c1>;
  547. status = "okay";
  548.  
  549. pmic: bd71837@4b {
  550. reg = <0x4b>;
  551. compatible = "rohm,bd71840", "rohm,bd71837";
  552. pinctrl-0 = <&pinctrl_pmic>;
  553. gpio_intr = <&gpio2 8 GPIO_ACTIVE_LOW>;
  554.  
  555. gpo {
  556. rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
  557. };
  558.  
  559. regulators {
  560. #address-cells = <1>;
  561. #size-cells = <0>;
  562.  
  563. bd71837,pmic-buck2-uses-i2c-dvs;
  564. bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
  565.  
  566. buck1_reg: regulator@0 {
  567. reg = <0>;
  568. regulator-compatible = "buck1";
  569. regulator-min-microvolt = <700000>;
  570. regulator-max-microvolt = <1300000>;
  571. regulator-boot-on;
  572. regulator-always-on;
  573. regulator-ramp-delay = <1250>;
  574. };
  575.  
  576. buck2_reg: regulator@1 {
  577. reg = <1>;
  578. regulator-compatible = "buck2";
  579. regulator-min-microvolt = <700000>;
  580. regulator-max-microvolt = <1300000>;
  581. regulator-boot-on;
  582. regulator-always-on;
  583. regulator-ramp-delay = <1250>;
  584. };
  585.  
  586. buck3_reg: regulator@2 {
  587. reg = <2>;
  588. regulator-compatible = "buck3";
  589. regulator-min-microvolt = <700000>;
  590. regulator-max-microvolt = <1300000>;
  591. };
  592.  
  593. buck4_reg: regulator@3 {
  594. reg = <3>;
  595. regulator-compatible = "buck4";
  596. regulator-min-microvolt = <700000>;
  597. regulator-max-microvolt = <1300000>;
  598. };
  599.  
  600. buck5_reg: regulator@4 {
  601. reg = <4>;
  602. regulator-compatible = "buck5";
  603. regulator-min-microvolt = <700000>;
  604. regulator-max-microvolt = <1350000>;
  605. regulator-boot-on;
  606. regulator-always-on;
  607. };
  608.  
  609. buck6_reg: regulator@5 {
  610. reg = <5>;
  611. regulator-compatible = "buck6";
  612. regulator-min-microvolt = <3000000>;
  613. regulator-max-microvolt = <3300000>;
  614. regulator-boot-on;
  615. regulator-always-on;
  616. };
  617.  
  618. buck7_reg: regulator@6 {
  619. reg = <6>;
  620. regulator-compatible = "buck7";
  621. regulator-min-microvolt = <1605000>;
  622. regulator-max-microvolt = <1995000>;
  623. regulator-boot-on;
  624. regulator-always-on;
  625. };
  626.  
  627. buck8_reg: regulator@7 {
  628. reg = <7>;
  629. regulator-compatible = "buck8";
  630. regulator-min-microvolt = <800000>;
  631. regulator-max-microvolt = <1400000>;
  632. regulator-boot-on;
  633. regulator-always-on;
  634. };
  635.  
  636. ldo1_reg: regulator@8 {
  637. reg = <8>;
  638. regulator-compatible = "ldo1";
  639. regulator-min-microvolt = <3000000>;
  640. regulator-max-microvolt = <3300000>;
  641. regulator-boot-on;
  642. regulator-always-on;
  643. };
  644.  
  645. ldo2_reg: regulator@9 {
  646. reg = <9>;
  647. regulator-compatible = "ldo2";
  648. regulator-min-microvolt = <900000>;
  649. regulator-max-microvolt = <900000>;
  650. regulator-boot-on;
  651. regulator-always-on;
  652. };
  653.  
  654. ldo3_reg: regulator@10 {
  655. reg = <10>;
  656. regulator-compatible = "ldo3";
  657. regulator-min-microvolt = <1800000>;
  658. regulator-max-microvolt = <3300000>;
  659. regulator-boot-on;
  660. regulator-always-on;
  661. };
  662.  
  663. ldo4_reg: regulator@11 {
  664. reg = <11>;
  665. regulator-compatible = "ldo4";
  666. regulator-min-microvolt = <900000>;
  667. regulator-max-microvolt = <1800000>;
  668. regulator-boot-on;
  669. regulator-always-on;
  670. };
  671.  
  672. ldo5_reg: regulator@12 {
  673. reg = <12>;
  674. regulator-compatible = "ldo5";
  675. regulator-min-microvolt = <1800000>;
  676. regulator-max-microvolt = <1800000>;
  677. regulator-always-on;
  678. };
  679.  
  680. ldo6_reg: regulator@13 {
  681. reg = <13>;
  682. regulator-compatible = "ldo6";
  683. regulator-min-microvolt = <900000>;
  684. regulator-max-microvolt = <1800000>;
  685. regulator-boot-on;
  686. regulator-always-on;
  687. };
  688. };
  689. };
  690.  
  691. dsi_lvds_bridge: sn65dsi84@2c {
  692. compatible = "ti,sn65dsi83";
  693. reg = <0x2c>;
  694. ti,dsi-lanes = <1>;
  695. ti,lvds-format = <1>;
  696. ti,lvds-bpp = <24>;
  697. ti,width-mm = <154>;
  698. ti,height-mm = <87>;
  699. enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  700. pinctrl-names = "default";
  701. pinctrl-0 = <&pinctrl_lvds>;
  702. status = "okay";
  703.  
  704. display-timings {
  705. lvds {
  706. clock-frequency = <33000000>;
  707. hactive = <800>;
  708. vactive = <480>;
  709. hback-porch = <40>;
  710. hfront-porch = <40>;
  711. vback-porch = <29>;
  712. vfront-porch = <13>;
  713. hsync-len = <48>;
  714. vsync-len = <3>;
  715. hsync-active = <0>;
  716. vsync-active = <0>;
  717. de-active = <1>;
  718. pixelclk-active = <0>;
  719. };
  720. };
  721.  
  722. port {
  723. lvds_from_dsi: endpoint {
  724. remote-endpoint = <&dsi_to_lvds>;
  725. };
  726. };
  727. };
  728. };
  729.  
  730. &i2c2 {
  731. clock-frequency = <100000>;
  732. pinctrl-names = "default";
  733. pinctrl-0 = <&pinctrl_i2c2>;
  734. status = "okay";
  735.  
  736. /* Capacitive touch controller */
  737. ft5x06_ts: ft5x06_ts@38 {
  738. status = "okay";
  739. compatible = "edt,edt-ft5x06";
  740. reg = <0x38>;
  741. reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
  742. pinctrl-names = "default";
  743. pinctrl-0 = <&pinctrl_captouch>;
  744. interrupt-parent = <&gpio1>;
  745. interrupts = <14 0>;
  746. touchscreen-size-x = <800>;
  747. touchscreen-size-y = <480>;
  748. touchscreen-inverted-x;
  749. touchscreen-inverted-y;
  750. };
  751.  
  752. ov5640_mipi1: ov5640_mipi1@3c {
  753. status = "okay";
  754. compatible = "ovti,ov5640_mipi";
  755. reg = <0x3c>;
  756. pinctrl-names = "default";
  757. pinctrl-0 = <&pinctrl_csi1>;
  758. clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
  759. clock-names = "csi_mclk";
  760. /* Disabled CLKO2, since DART-MX8MM camera expansion board uses
  761. * its own oscillator. Enable CLK02 if your desing requres it
  762. */
  763. #if 0
  764. assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
  765. <&clk IMX8MM_CLK_CLKO1_DIV>;
  766. assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
  767. assigned-clock-rates = <0>, <24000000>;
  768. #endif
  769. csi_id = <0>;
  770. pwn-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
  771. rst-gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>;
  772. mclk = <24000000>;
  773. mclk_source = <0>;
  774. port {
  775. ov5640_mipi1_ep: endpoint {
  776. remote-endpoint = <&mipi1_sensor_ep>;
  777. };
  778. };
  779. };
  780.  
  781. /* DS1337 RTC module */
  782. rtc@0x68 {
  783. status = "okay";
  784. compatible = "dallas,ds1337";
  785. reg = <0x68>;
  786. pinctrl-names = "default";
  787. pinctrl-0 = <&pinctrl_rtc>;
  788. interrupt-parent = <&gpio1>;
  789. interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
  790. };
  791. };
  792.  
  793.  
  794. &i2c3 {
  795. clock-frequency = <100000>;
  796. pinctrl-names = "default";
  797. pinctrl-0 = <&pinctrl_i2c3>;
  798. status = "okay";
  799.  
  800. wm8904: codec@1a {
  801. compatible = "wlf,wm8904";
  802. reg = <0x1a>;
  803. clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  804. clock-names = "mclk";
  805. DCVDD-supply = <&ldo5_reg>;
  806. DBVDD-supply = <&reg_audio>;
  807. AVDD-supply = <&ldo5_reg>;
  808. CPVDD-supply = <&ldo5_reg>;
  809. MICVDD-supply = <&ldo5_reg>;
  810. status = "okay";
  811. gpio-cfg = <
  812. 0x0018 /* GPIO1 => DMIC_CLK */
  813. 0xffff /* GPIO2 => don't touch */
  814. 0xffff /* GPIO3 => don't touch */
  815. 0xffff /* GPIO4 => don't touch */
  816. >;
  817. };
  818. };
  819.  
  820. &i2c4 {
  821. clock-frequency = <100000>;
  822. pinctrl-names = "default";
  823. pinctrl-0 = <&pinctrl_i2c4>;
  824. status = "okay";
  825. };
  826.  
  827. &csi1_bridge {
  828. fsl,mipi-mode;
  829. status = "okay";
  830. port {
  831. csi1_ep: endpoint {
  832. remote-endpoint = <&csi1_mipi_ep>;
  833. };
  834. };
  835. };
  836.  
  837. &mipi_csi_1 {
  838. #address-cells = <1>;
  839. #size-cells = <0>;
  840. status = "okay";
  841. port {
  842. mipi1_sensor_ep: endpoint1 {
  843. remote-endpoint = <&ov5640_mipi1_ep>;
  844. data-lanes = <2>;
  845. csis-hs-settle = <13>;
  846. csis-clk-settle = <2>;
  847. csis-wclk;
  848. };
  849.  
  850. csi1_mipi_ep: endpoint2 {
  851. remote-endpoint = <&csi1_ep>;
  852. };
  853. };
  854. };
  855.  
  856. &mu {
  857. status = "okay";
  858. };
  859.  
  860. &rpmsg{
  861. /*
  862. * 64K for one rpmsg instance:
  863. * --0xb8000000~0xb800ffff: pingpong
  864. */
  865. vdev-nums = <1>;
  866. reg = <0x0 0xb8000000 0x0 0x10000>;
  867. status = "okay";
  868. };
  869.  
  870. &sai3 {
  871. pinctrl-names = "default";
  872. pinctrl-0 = <&pinctrl_sai3>;
  873. assigned-clocks = <&clk IMX8MM_CLK_SAI3_SRC>,
  874. <&clk IMX8MM_CLK_SAI3_DIV>;
  875. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  876. assigned-clock-rates = <0>, <1536000>;
  877. status = "okay";
  878. };
  879.  
  880. &sai5 {
  881. pinctrl-names = "default";
  882. pinctrl-0 = <&pinctrl_sai5>;
  883. assigned-clocks = <&clk IMX8MM_CLK_SAI5_SRC>,
  884. <&clk IMX8MM_CLK_SAI5_DIV>;
  885. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  886. assigned-clock-rates = <0>, <1536000>;
  887. #sound-dai-cells = <0>;
  888. status = "okay";
  889. };
  890.  
  891. &spdif1 {
  892. pinctrl-names = "default";
  893. pinctrl-0 = <&pinctrl_spdif1>;
  894. assigned-clocks = <&clk IMX8MM_CLK_SPDIF1_SRC>,
  895. <&clk IMX8MM_CLK_SPDIF1_DIV>;
  896. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  897. assigned-clock-rates = <0>, <24576000>;
  898. clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_24M>,
  899. <&clk IMX8MM_CLK_SPDIF1_DIV>, <&clk IMX8MM_CLK_DUMMY>,
  900. <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
  901. <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_DUMMY>,
  902. <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
  903. <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
  904. clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
  905. "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
  906. status = "disabled";
  907. };
  908.  
  909. &fec1 {
  910. pinctrl-names = "default";
  911. pinctrl-0 = <&pinctrl_fec1>;
  912. phy-mode = "rgmii";
  913. phy-handle = <&ethphy0>;
  914. phy-supply = <&reg_eth_phy>;
  915. phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  916. phy-reset-duration = <10>;
  917. fsl,magic-packet;
  918. status = "okay";
  919.  
  920. mdio {
  921. #address-cells = <1>;
  922. #size-cells = <0>;
  923.  
  924. ethphy0: ethernet-phy@0 {
  925. compatible = "ethernet-phy-ieee802.3-c22";
  926. reg = <0>;
  927. at803x,led-act-blind-workaround;
  928. at803x,eee-okay;
  929. at803x,vddio-1p8v;
  930. };
  931. };
  932. };
  933.  
  934. &pcie0 {
  935. pinctrl-names = "default";
  936. pinctrl-0 = <&pinctrl_pcie0>;
  937. reset-gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
  938. ext_osc = <1>;
  939. status = "okay";
  940. };
  941.  
  942. /* Console */
  943. &uart1 {
  944. pinctrl-names = "default";
  945. pinctrl-0 = <&pinctrl_uart1>;
  946. status = "okay";
  947. };
  948.  
  949. /* Header */
  950. &uart2 {
  951. pinctrl-names = "default";
  952. pinctrl-0 = <&pinctrl_uart2>;
  953. status = "okay";
  954. };
  955.  
  956. /* Header */
  957. &uart3 {
  958. pinctrl-names = "default";
  959. pinctrl-0 = <&pinctrl_uart3>;
  960. status = "okay";
  961. };
  962.  
  963. /* BT */
  964. &uart4 {
  965. pinctrl-names = "default";
  966. pinctrl-0 = <&pinctrl_uart4>;
  967. assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>;
  968. assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
  969. uart-has-rtscts;
  970. status = "okay";
  971. };
  972.  
  973. &usbotg1 {
  974. dr_mode = "otg";
  975. picophy,pre-emp-curr-control = <3>;
  976. picophy,dc-vol-level-adjust = <7>;
  977. status = "okay";
  978. };
  979.  
  980. &usbotg2 {
  981. dr_mode = "host";
  982. picophy,pre-emp-curr-control = <3>;
  983. picophy,dc-vol-level-adjust = <7>;
  984. status = "okay";
  985. };
  986.  
  987. /* WIFI */
  988. &usdhc1 {
  989. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  990. pinctrl-0 = <&pinctrl_usdhc1>;
  991. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  992. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  993. bus-width = <4>;
  994. vmmc-supply = <&reg_wifi_en>;
  995. status = "okay";
  996. };
  997.  
  998. /* SD */
  999. &usdhc2 {
  1000. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1001. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  1002. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  1003. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  1004. cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  1005. bus-width = <4>;
  1006. vmmc-supply = <&reg_usdhc2_vmmc>;
  1007. status = "okay";
  1008. };
  1009.  
  1010. /* EMMC */
  1011. &usdhc3 {
  1012. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1013. pinctrl-0 = <&pinctrl_usdhc3>;
  1014. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  1015. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  1016. bus-width = <8>;
  1017. non-removable;
  1018. status = "okay";
  1019. };
  1020.  
  1021. &wdog1 {
  1022. pinctrl-names = "default";
  1023. pinctrl-0 = <&pinctrl_wdog>;
  1024. fsl,ext-reset-output;
  1025. status = "okay";
  1026. };
  1027.  
  1028. &A53_0 {
  1029. arm-supply = <&buck2_reg>;
  1030. };
  1031.  
  1032. &gpu {
  1033. status = "okay";
  1034. };
  1035.  
  1036. &vpu_g1 {
  1037. status = "okay";
  1038. };
  1039.  
  1040. &vpu_g2 {
  1041. status = "okay";
  1042. };
  1043.  
  1044. &vpu_h1 {
  1045. status = "okay";
  1046. };
  1047.  
  1048. &micfil {
  1049. pinctrl-names = "default";
  1050. pinctrl-0 = <&pinctrl_pdm>;
  1051. assigned-clocks = <&clk IMX8MM_CLK_PDM_SRC>, <&clk IMX8MM_CLK_PDM_DIV>;
  1052. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  1053. assigned-clock-rates = <0>, <196608000>;
  1054. status = "disabled";
  1055. };
  1056.  
  1057. &lcdif {
  1058. status = "okay";
  1059. };
  1060.  
  1061. &mipi_dsi {
  1062. status = "okay";
  1063.  
  1064. port@1 {
  1065. dsi_to_lvds: endpoint {
  1066. remote-endpoint = <&lvds_from_dsi>;
  1067. };
  1068. };
  1069. };
  1070.  
  1071. &ecspi1 {
  1072. pinctrl-names = "default";
  1073. pinctrl-0 = <&pinctrl_ecspi1>;
  1074. cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>,
  1075. <&gpio1 12 GPIO_ACTIVE_HIGH>;
  1076. fsl,spi-num-chipselects = <2>;
  1077. /delete-property/ dmas;
  1078. /delete-property/ dma-names;
  1079. status = "okay";
  1080.  
  1081. /* Resistive touch controller */
  1082. ads7846@0 {
  1083. reg = <0>;
  1084. compatible = "ti,ads7846";
  1085. pinctrl-names = "default";
  1086. pinctrl-0 = <&pinctrl_restouch>;
  1087. interrupt-parent = <&gpio1>;
  1088. interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  1089. spi-max-frequency = <1500000>;
  1090. pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
  1091. ti,x-min = /bits/ 16 <125>;
  1092. ti,x-max = /bits/ 16 <4008>;
  1093. ti,y-min = /bits/ 16 <282>;
  1094. ti,y-max = /bits/ 16 <3864>;
  1095. ti,x-plate-ohms = /bits/ 16 <180>;
  1096. ti,pressure-max = /bits/ 16 <255>;
  1097. ti,debounce-max = /bits/ 16 <10>;
  1098. ti,debounce-tol = /bits/ 16 <3>;
  1099. ti,debounce-rep = /bits/ 16 <1>;
  1100. ti,settle-delay-usec = /bits/ 16 <150>;
  1101. ti,keep-vref-on;
  1102. wakeup-source;
  1103. status = "disabled";
  1104. };
  1105.  
  1106. can0: can@1 {
  1107. compatible = "microchip,mcp2517fd";
  1108. reg = <1>;
  1109. pinctrl-names = "default";
  1110. pinctrl-0 = <&pinctrl_can>;
  1111. clocks = <&can0_osc>;
  1112. interrupt-parent = <&gpio1>;
  1113. interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
  1114. spi-max-frequency = <20000000>;
  1115. status = "okay";
  1116. };
  1117. };
  1118.  
  1119. &flexspi {
  1120. pinctrl-names = "default";
  1121. pinctrl-0 = <&pinctrl_flexspi0>;
  1122. status = "disabled";
  1123. };
  1124.  
  1125. &snvs_rtc {
  1126. status = "disabled";
  1127. };
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