module lab3
(
    input logic clk, reset, in,
    output logic [2:0] out
);

    enum logic [2:0] {S0,S1,S2,S3,S4,S5,S6,S7} state, next_state;


    always_ff @ (posedge clk or negedge reset) begin
        if (!reset) state <= S0;
        else state <= next_state;
    end


    always_comb begin
        case (state)
                S0: if (in)
                        next_state = S1;
                    else
                        next_state = S6;
                S1: if (in)
                        next_state = S2;
                    else
                        next_state = S7;
                S2: if (in)
                        next_state = S3;
                    else
                        next_state = S0;
                S3: if (in)
                        next_state = S4;
                    else
                        next_state = S1;
                S4: if (in)
                        next_state = S5;
                    else
                        next_state = S2;
                S5: if (in)
                        next_state = S6;
                    else
                        next_state = S3;
                S6: if (in)
                        next_state = S7;
                    else
                        next_state = S4;
                S7: if (in)
                        next_state = S0;
                    else
                        next_state = S5;
            endcase
    end

    always_comb begin
        case (state)
            S0: out = 3'b000;
            S1: out = 3'b001;
            S2: out = 3'b011;
            S3: out = 3'b010;
            S4: out = 3'b110;
            S5: out = 3'b111;
            S6: out = 3'b101;
            S7: out = 3'b100;
            default: out = 3'b000;
        endcase
    end

endmodule