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varli_ketanpl

AC_LAB1_EX3

Oct 11th, 2023 (edited)
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  1. module add6(
  2.     output[6:0] sum,
  3.     input[5:0] a, b);
  4.    
  5.     wire c_in1, c_in2;
  6.     add4(sum[3:0], c_in1, a[3:0], b[3:0]);
  7.     full_adder f1(sum[4], c_in2, a[4], b[4], c_in1);
  8.     full_adder f2(sum[5], sum[6], a[5], b[5], c_in2);
  9. endmodule
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