20130515_DigitalDesign_Test_3

module counter(input ck,re,output reg [7:0]seg,led);

reg [24:0]div;
reg ck_1;
reg [2:0]Q ;

always @(posedge ck,negedge re)
begin
    if(!re) begin div <= 0 ; ck_1 <= 0 ; end
    else if(div == 24999999) begin div <= 0 ; ck_1 <= ~ck_1 ; end
    else div <= div + 1 ;
end

always @(posedge ck_1,negedge re)
begin
    if(!re) Q <= 3'b111 ;
    else if(Q == 3'b000) Q <= 3'b111 ;
    else Q <= Q - 1 ;
        case(Q)
        3'b000:       begin
                        led <= 8'b11111110 ;
                        seg <= 8'b00000010 ;
                  end
        3'b001:
                  begin
                        led <= 8'b11111101 ;
                        seg <= 8'b10011110 ;
                  end
        3'b010:
                  begin
                        led <= 8'b11111011 ;
                        seg <= 8'b00100100 ;
                  end
        3'b011:
                  begin
                        led <= 8'b11110111 ;
                        seg <= 8'b00001100 ;
                  end
        3'b100:
                  begin
                        led <= 8'b11101111 ;
                        seg <= 8'b10011000 ;
                  end
        3'b101:
                  begin
                        led <= 8'b11011111 ;
                        seg <= 8'b01001000 ;
                  end
        3'b110:
                  begin
                        led <= 8'b10111111 ;
                        seg <= 8'b01000000 ;
                  end
        3'b111:
                  begin
                        led <= 8'b01111111 ;
                        seg <= 8'b00011110 ;
                  end
        default:
                  begin
                        led <= 8'b01111111 ;
                        seg <= 8'b00011110 ;
                  end
        endcase
end

endmodule