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kamst-ir-gateway-log

WhiZTiM
Nov 13th, 2024
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  1.  
  2. [15:10:56]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  3. [15:10:56]configsip: 0, SPIWP:0xee
  4. [15:10:56]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  5. [15:10:56]mode:DIO, clock div:1
  6. [15:10:56]load:0x3fff0018,len:4
  7. [15:10:56]load:0x7fbf005c,len:84
  8. [15:10:56]load:0x296b6e28,len:694315132
  9. [15:10:56]1150 mmu set 00010000, pos 00010000
  10. [15:10:56]1150 mmu set 00020000, pos 00020000
  11. [15:10:56]1150 mmu set 00030000, pos 00030000
  12. [15:10:56]1150 mmu set 00040000, pos 00040000
  13. [15:10:56]1150 mmu set 00050000, pos 00050000
  14. [15:10:56]1150 mmu set 00060000, pos 00060000
  15. [15:10:56]1150 mmu set 00070000, pos 00070000
  16. [15:10:56]1150 mmu set 00080000, pos 00080000
  17. [15:10:56]1150 mmu set 00090000, pos 00090000
  18. [15:10:56]1150 mmu set 000a0000, pos 000a0000
  19. [15:10:57]1150 mmu set 000b0000, pos 000b0000
  20. [15:10:57]1150 mmu set 000c0000, pos 000c0000
  21. [15:10:57]1150 mmu set 000d0000, pos 000d0000
  22. [15:10:57]1150 mmu set 000e0000, pos 000e0000
  23. [15:10:57]1150 mmu set 000f0000, pos 000f0000
  24. [15:10:57]1150 mmu set 00100000, pos 00100000
  25. [15:10:57]1150 mmu set 00110000, pos 00110000
  26. [15:10:57]ets Jul 29 2019 12:21:46
  27. [15:10:57]
  28. [15:10:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  29. [15:10:57]configsip: 0, SPIWP:0xee
  30. [15:10:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  31. [15:10:57]mode:DIO, clock div:1
  32. [15:10:57]load:0x3fff0018,len:4
  33. [15:10:57]load:0x7fbf005c,len:84
  34. [15:10:57]load:0x296b6e28,len:694315132
  35. [15:10:57]1150 mmu set 00010000, pos 00010000
  36. [15:10:57]1150 mmu set 00020000, pos 00020000
  37. [15:10:57]1150 mmu set 00030000, pos 00030000
  38. [15:10:57]1150 mmu set 00040000, pos 00040000
  39. [15:10:57]1150 mmu set 00050000, pos 00050000
  40. [15:10:57]1150 mmu set 00060000, pos 00060000
  41. [15:10:57]1150 mmu set 00070000, pos 00070000
  42. [15:10:57]1150 mmu set 00080000, pos 00080000
  43. [15:10:57]1150 mmu set 00090000, pos 00090000
  44. [15:10:57]1150 mmu set 000a0000, pos 000a0000
  45. [15:10:57]1150 mmu set 000b0000, pos 000b0000
  46. [15:10:57]1150 mmu set 000c0000, pos 000c0000
  47. [15:10:57]1150 mmu set 000d0000, pos 000d0000
  48. [15:10:57]1150 mmu set 000e0000, pos 000e0000
  49. [15:10:57]1150 mmu set 000f0000, pos 000f0000
  50. [15:10:57]1150 mmu set 00100000, pos 00100000
  51. [15:10:57]1150 mmu set 00110000, pos 00110000
  52. [15:10:57]ets Jul 29 2019 12:21:46
  53. [15:10:57]
  54. [15:10:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  55. [15:10:57]configsip: 0, SPIWP:0xee
  56. [15:10:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  57. [15:10:57]mode:DIO, clock div:1
  58. [15:10:57]load:0x3fff0018,len:4
  59. [15:10:57]load:0x7fbf005c,len:84
  60. [15:10:57]load:0x296b6e28,len:694315132
  61. [15:10:57]1150 mmu set 00010000, pos 00010000
  62. [15:10:57]1150 mmu set 00020000, pos 00020000
  63. [15:10:57]1150 mmu set 00030000, pos 00030000
  64. [15:10:57]1150 mmu set 00040000, pos 00040000
  65. [15:10:57]1150 mmu set 00050000, pos 00050000
  66. [15:10:57]1150 mmu set 00060000, pos 00060000
  67. [15:10:57]1150 mmu set 00070000, pos 00070000
  68. [15:10:57]1150 mmu set 00080000, pos 00080000
  69. [15:10:57]1150 mmu set 00090000, pos 00090000
  70. [15:10:57]1150 mmu set 000a0000, pos 000a0000
  71. [15:10:57]1150 mmu set 000b0000, pos 000b0000
  72. [15:10:57]1150 mmu set 000c0000, pos 000c0000
  73. [15:10:57]1150 mmu set 000d0000, pos 000d0000
  74. [15:10:57]1150 mmu set 000e0000, pos 000e0000
  75. [15:10:57]1150 mmu set 000f0000, pos 000f0000
  76. [15:10:57]1150 mmu set 00100000, pos 00100000
  77. [15:10:57]1150 mmu set 00110000, pos 00110000
  78. [15:10:57]ets Jul 29 2019 12:21:46
  79. [15:10:57]
  80. [15:10:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  81. [15:10:57]configsip: 0, SPIWP:0xee
  82. [15:10:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  83. [15:10:57]mode:DIO, clock div:1
  84. [15:10:57]load:0x3fff0018,len:4
  85. [15:10:57]load:0x7fbf005c,len:84
  86. [15:10:57]load:0x296b6e28,len:694315116
  87. [15:10:57]1150 mmu set 00010000, pos 00010000
  88. [15:10:57]1150 mmu set 00020000, pos 00020000
  89. [15:10:57]1150 mmu set 00030000, pos 00030000
  90. [15:10:57]1150 mmu set 00040000, pos 00040000
  91. [15:10:57]1150 mmu set 00050000, pos 00050000
  92. [15:10:57]1150 mmu set 00060000, pos 00060000
  93. [15:10:57]1150 mmu set 00070000, pos 00070000
  94. [15:10:58]1150 mmu set 00080000, pos 00080000
  95. [15:10:58]1150 mmu set 00090000, pos 00090000
  96. [15:10:58]1150 mmu set 000a0000, pos 000a0000
  97. [15:10:58]1150 mmu set 000b0000, pos 000b0000
  98. [15:10:58]1150 mmu set 000c0000, pos 000c0000
  99. [15:10:58]1150 mmu set 000d0000, pos 000d0000
  100. [15:10:58]1150 mmu set 000e0000, pos 000e0000
  101. [15:10:58]1150 mmu set 000f0000, pos 000f0000
  102. [15:10:58]1150 mmu set 00100000, pos 00100000
  103. [15:10:58]1150 mmu set 00110000, pos 00110000
  104. [15:10:58]ets Jul 29 2019 12:21:46
  105. [15:10:58]
  106. [15:10:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  107. [15:10:58]configsip: 0, SPIWP:0xee
  108. [15:10:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  109. [15:10:58]mode:DIO, clock div:1
  110. [15:10:58]load:0x3fff0018,len:4
  111. [15:10:58]load:0x7fbf005c,len:84
  112. [15:10:58]load:0x296f6e28,len:694315132
  113. [15:10:58]1150 mmu set 00010000, pos 00010000
  114. [15:10:58]1150 mmu set 00020000, pos 00020000
  115. [15:10:58]1150 mmu set 00030000, pos 00030000
  116. [15:10:58]1150 mmu set 00040000, pos 00040000
  117. [15:10:58]1150 mmu set 00050000, pos 00050000
  118. [15:10:58]1150 mmu set 00060000, pos 00060000
  119. [15:10:58]1150 mmu set 00070000, pos 00070000
  120. [15:10:58]1150 mmu set 00080000, pos 00080000
  121. [15:10:58]1150 mmu set 00090000, pos 00090000
  122. [15:10:58]1150 mmu set 000a0000, pos 000a0000
  123. [15:10:58]1150 mmu set 000b0000, pos 000b0000
  124. [15:10:58]1150 mmu set 000c0000, pos 000c0000
  125. [15:10:58]1150 mmu set 000d0000, pos 000d0000
  126. [15:10:58]1150 mmu set 000e0000, pos 000e0000
  127. [15:10:58]1150 mmu set 000f0000, pos 000f0000
  128. [15:10:58]1150 mmu set 00100000, pos 00100000
  129. [15:10:58]1150 mmu set 00110000, pos 00110000
  130. [15:10:58]ets Jul 29 2019 12:21:46
  131. [15:10:58]
  132. [15:10:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  133. [15:10:58]configsip: 0, SPIWP:0xee
  134. [15:10:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  135. [15:10:58]mode:DIO, clock div:1
  136. [15:10:58]load:0x3fff0018,len:4
  137. [15:10:58]load:0x7fbf005c,len:84
  138. [15:10:58]load:0x296b6e28,len:694315132
  139. [15:10:58]1150 mmu set 00010000, pos 00010000
  140. [15:10:58]1150 mmu set 00020000, pos 00020000
  141. [15:10:58]1150 mmu set 00030000, pos 00030000
  142. [15:10:58]1150 mmu set 00040000, pos 00040000
  143. [15:10:58]1150 mmu set 00050000, pos 00050000
  144. [15:10:58]1150 mmu set 00060000, pos 00060000
  145. [15:10:58]1150 mmu set 00070000, pos 00070000
  146. [15:10:58]1150 mmu set 00080000, pos 00080000
  147. [15:10:58]1150 mmu set 00090000, pos 00090000
  148. [15:10:58]1150 mmu set 000a0000, pos 000a0000
  149. [15:10:58]1150 mmu set 000b0000, pos 000b0000
  150. [15:10:58]1150 mmu set 000c0000, pos 000c0000
  151. [15:10:58]1150 mmu set 000d0000, pos 000d0000
  152. [15:10:58]1150 mmu set 000e0000, pos 000e0000
  153. [15:10:58]1150 mmu set 000f0000, pos 000f0000
  154. [15:10:58]1150 mmu set 00100000, pos 00100000
  155. [15:10:58]1150 mmu set 00110000, pos 00110000
  156. [15:10:58]ets Jul 29 2019 12:21:46
  157. [15:10:58]
  158. [15:10:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  159. [15:10:58]configsip: 0, SPIWP:0xee
  160. [15:10:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  161. [15:10:58]mode:DIO, clock div:1
  162. [15:10:58]load:0x3fff0018,len:4
  163. [15:10:58]load:0x7fbf005c,len:84
  164. [15:10:58]load:0x296b6e28,len:694315116
  165. [15:10:58]1150 mmu set 00010000, pos 00010000
  166. [15:10:58]1150 mmu set 00020000, pos 00020000
  167. [15:10:58]1150 mmu set 00030000, pos 00030000
  168. [15:10:58]1150 mmu set 00040000, pos 00040000
  169. [15:10:59]1150 mmu set 00050000, pos 00050000
  170. [15:10:59]1150 mmu set 00060000, pos 00060000
  171. [15:10:59]1150 mmu set 00070000, pos 00070000
  172. [15:10:59]1150 mmu set 00080000, pos 00080000
  173. [15:10:59]1150 mmu set 00090000, pos 00090000
  174. [15:10:59]1150 mmu set 000a0000, pos 000a0000
  175. [15:10:59]1150 mmu set 000b0000, pos 000b0000
  176. [15:10:59]1150 mmu set 000c0000, pos 000c0000
  177. [15:10:59]1150 mmu set 000d0000, pos 000d0000
  178. [15:10:59]1150 mmu set 000e0000, pos 000e0000
  179. [15:10:59]1150 mmu set 000f0000, pos 000f0000
  180. [15:10:59]1150 mmu set 00100000, pos 00100000
  181. [15:10:59]1150 mmu set 00110000, pos 00110000
  182. [15:10:59]ets Jul 29 2019 12:21:46
  183. [15:10:59]
  184. [15:10:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  185. [15:10:59]configsip: 0, SPIWP:0xee
  186. [15:10:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  187. [15:10:59]mode:DIO, clock div:1
  188. [15:10:59]load:0x3fff0018,len:4
  189. [15:10:59]load:0x7fbf005c,len:84
  190. [15:10:59]load:0x296b6e28,len:694315116
  191. [15:10:59]1150 mmu set 00010000, pos 00010000
  192. [15:10:59]1150 mmu set 00020000, pos 00020000
  193. [15:10:59]1150 mmu set 00030000, pos 00030000
  194. [15:10:59]1150 mmu set 00040000, pos 00040000
  195. [15:10:59]1150 mmu set 00050000, pos 00050000
  196. [15:10:59]1150 mmu set 00060000, pos 00060000
  197. [15:10:59]1150 mmu set 00070000, pos 00070000
  198. [15:10:59]1150 mmu set 00080000, pos 00080000
  199. [15:10:59]1150 mmu set 00090000, pos 00090000
  200. [15:10:59]1150 mmu set 000a0000, pos 000a0000
  201. [15:10:59]1150 mmu set 000b0000, pos 000b0000
  202. [15:10:59]1150 mmu set 000c0000, pos 000c0000
  203. [15:10:59]1150 mmu set 000d0000, pos 000d0000
  204. [15:10:59]1150 mmu set 000e0000, pos 000e0000
  205. [15:10:59]1150 mmu set 000f0000, pos 000f0000
  206. [15:10:59]1150 mmu set 00100000, pos 00100000
  207. [15:10:59]1150 mmu set 00110000, pos 00110000
  208. [15:10:59]ets Jul 29 2019 12:21:46
  209. [15:10:59]
  210. [15:10:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  211. [15:10:59]configsip: 0, SPIWP:0xee
  212. [15:10:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  213. [15:10:59]mode:DIO, clock div:1
  214. [15:10:59]load:0x3fff0018,len:4
  215. [15:10:59]load:0x7fbf005c,len:84
  216. [15:10:59]load:0x296f6e28,len:694315132
  217. [15:10:59]1150 mmu set 00010000, pos 00010000
  218. [15:10:59]1150 mmu set 00020000, pos 00020000
  219. [15:10:59]1150 mmu set 00030000, pos 00030000
  220. [15:10:59]1150 mmu set 00040000, pos 00040000
  221. [15:10:59]1150 mmu set 00050000, pos 00050000
  222. [15:10:59]1150 mmu set 00060000, pos 00060000
  223. [15:10:59]1150 mmu set 00070000, pos 00070000
  224. [15:10:59]1150 mmu set 00080000, pos 00080000
  225. [15:10:59]1150 mmu set 00090000, pos 00090000
  226. [15:10:59]1150 mmu set 000a0000, pos 000a0000
  227. [15:10:59]1150 mmu set 000b0000, pos 000b0000
  228. [15:10:59]1150 mmu set 000c0000, pos 000c0000
  229. [15:10:59]1150 mmu set 000d0000, pos 000d0000
  230. [15:10:59]1150 mmu set 000e0000, pos 000e0000
  231. [15:10:59]1150 mmu set 000f0000, pos 000f0000
  232. [15:10:59]1150 mmu set 00100000, pos 00100000
  233. [15:10:59]1150 mmu set 00110000, pos 00110000
  234. [15:10:59]ets Jul 29 2019 12:21:46
  235. [15:10:59]
  236. [15:10:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  237. [15:10:59]configsip: 0, SPIWP:0xee
  238. [15:10:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  239. [15:10:59]mode:DIO, clock div:1
  240. [15:10:59]load:0x3fff0018,len:4
  241. [15:10:59]load:0x7fbf005c,len:84
  242. [15:10:59]load:0x296b6e28,len:694315132
  243. [15:10:59]1150 mmu set 00010000, pos 00010000
  244. [15:11:00]1150 mmu set 00020000, pos 00020000
  245. [15:11:00]1150 mmu set 00030000, pos 00030000
  246. [15:11:00]1150 mmu set 00040000, pos 00040000
  247. [15:11:00]1150 mmu set 00050000, pos 00050000
  248. [15:11:00]1150 mmu set 00060000, pos 00060000
  249. [15:11:00]1150 mmu set 00070000, pos 00070000
  250. [15:11:00]1150 mmu set 00080000, pos 00080000
  251. [15:11:00]1150 mmu set 00090000, pos 00090000
  252. [15:11:00]1150 mmu set 000a0000, pos 000a0000
  253. [15:11:00]1150 mmu set 000b0000, pos 000b0000
  254. [15:11:00]1150 mmu set 000c0000, pos 000c0000
  255. [15:11:00]1150 mmu set 000d0000, pos 000d0000
  256. [15:11:00]1150 mmu set 000e0000, pos 000e0000
  257. [15:11:00]1150 mmu set 000f0000, pos 000f0000
  258. [15:11:00]1150 mmu set 00100000, pos 00100000
  259. [15:11:00]1150 mmu set 00110000, pos 00110000
  260. [15:11:00]ets Jul 29 2019 12:21:46
  261. [15:11:00]
  262. [15:11:00]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  263. [15:11:00]configsip: 0, SPIWP:0xee
  264. [15:11:00]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  265. [15:11:00]mode:DIO, clock div:1
  266. [15:11:00]load:0x3fff0018,len:4
  267. [15:11:00]load:0x7fbf005c,len:84
  268. [15:11:00]load:0x296b6e28,len:694315132
  269. [15:11:00]1150 mmu set 00010000, pos 00010000
  270. [15:11:00]1150 mmu set 00020000, pos 00020000
  271. [15:11:00]1150 mmu set 00030000, pos 00030000
  272. [15:11:00]1150 mmu set 00040000, pos 00040000
  273. [15:11:00]1150 mmu set 00050000, pos 00050000
  274. [15:11:00]1150 mmu set 00060000, pos 00060000
  275. [15:11:00]1150 mmu set 00070000, pos 00070000
  276. [15:11:00]1150 mmu set 00080000, pos 00080000
  277. [15:11:00]1150 mmu set 00090000, pos 00090000
  278. [15:11:00]1150 mmu set 000a0000, pos 000a0000
  279. [15:11:00]1150 mmu set 000b0000, pos 000b0000
  280. [15:11:00]1150 mmu set 000c0000, pos 000c0000
  281. [15:11:00]1150 mmu set 000d0000, pos 000d0000
  282. [15:11:00]1150 mmu set 000e0000, pos 000e0000
  283. [15:11:00]1150 mmu set 000f0000, pos 000f0000
  284. [15:11:00]1150 mmu set 00100000, pos 00100000
  285. [15:11:00]1150 mmu set 00110000, pos 00110000
  286. [15:11:00]ets Jul 29 2019 12:21:46
  287. [15:11:00]
  288. [15:11:00]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  289. [15:11:00]configsip: 0, SPIWP:0xee
  290. [15:11:00]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  291. [15:11:00]mode:DIO, clock div:1
  292. [15:11:00]load:0x3fff0018,len:4
  293. [15:11:00]load:0x7fbf005c,len:84
  294. [15:11:00]load:0x296b6e28,len:694315132
  295. [15:11:00]1150 mmu set 00010000, pos 00010000
  296. [15:11:00]1150 mmu set 00020000, pos 00020000
  297. [15:11:00]1150 mmu set 00030000, pos 00030000
  298. [15:11:00]1150 mmu set 00040000, pos 00040000
  299. [15:11:00]1150 mmu set 00050000, pos 00050000
  300. [15:11:00]1150 mmu set 00060000, pos 00060000
  301. [15:11:00]1150 mmu set 00070000, pos 00070000
  302. [15:11:00]1150 mmu set 00080000, pos 00080000
  303. [15:11:00]1150 mmu set 00090000, pos 00090000
  304. [15:11:00]1150 mmu set 000a0000, pos 000a0000
  305. [15:11:00]1150 mmu set 000b0000, pos 000b0000
  306. [15:11:00]1150 mmu set 000c0000, pos 000c0000
  307. [15:11:00]1150 mmu set 000d0000, pos 000d0000
  308. [15:11:00]1150 mmu set 000e0000, pos 000e0000
  309. [15:11:00]1150 mmu set 000f0000, pos 000f0000
  310. [15:11:00]1150 mmu set 00100000, pos 00100000
  311. [15:11:01]1150 mmu set 00110000, pos 00110000
  312. [15:11:01]ets Jul 29 2019 12:21:46
  313. [15:11:01]
  314. [15:11:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  315. [15:11:01]configsip: 0, SPIWP:0xee
  316. [15:11:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  317. [15:11:01]mode:DIO, clock div:1
  318. [15:11:01]load:0x3fff0018,len:4
  319. [15:11:01]load:0x7fbf005c,len:84
  320. [15:11:01]load:0x296b6e28,len:694315132
  321. [15:11:01]1150 mmu set 00010000, pos 00010000
  322. [15:11:01]1150 mmu set 00020000, pos 00020000
  323. [15:11:01]1150 mmu set 00030000, pos 00030000
  324. [15:11:01]1150 mmu set 00040000, pos 00040000
  325. [15:11:01]1150 mmu set 00050000, pos 00050000
  326. [15:11:01]1150 mmu set 00060000, pos 00060000
  327. [15:11:01]1150 mmu set 00070000, pos 00070000
  328. [15:11:01]1150 mmu set 00080000, pos 00080000
  329. [15:11:01]1150 mmu set 00090000, pos 00090000
  330. [15:11:01]1150 mmu set 000a0000, pos 000a0000
  331. [15:11:01]1150 mmu set 000b0000, pos 000b0000
  332. [15:11:01]1150 mmu set 000c0000, pos 000c0000
  333. [15:11:01]1150 mmu set 000d0000, pos 000d0000
  334. [15:11:01]1150 mmu set 000e0000, pos 000e0000
  335. [15:11:01]1150 mmu set 000f0000, pos 000f0000
  336. [15:11:01]1150 mmu set 00100000, pos 00100000
  337. [15:11:01]1150 mmu set 00110000, pos 00110000
  338. [15:11:01]ets Jul 29 2019 12:21:46
  339. [15:11:01]
  340. [15:11:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  341. [15:11:01]configsip: 0, SPIWP:0xee
  342. [15:11:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  343. [15:11:01]mode:DIO, clock div:1
  344. [15:11:01]load:0x3fff0018,len:4
  345. [15:11:01]load:0x7fbf005c,len:84
  346. [15:11:01]load:0x296b6e28,len:694315132
  347. [15:11:01]1150 mmu set 00010000, pos 00010000
  348. [15:11:01]1150 mmu set 00020000, pos 00020000
  349. [15:11:01]1150 mmu set 00030000, pos 00030000
  350. [15:11:01]1150 mmu set 00040000, pos 00040000
  351. [15:11:01]1150 mmu set 00050000, pos 00050000
  352. [15:11:01]1150 mmu set 00060000, pos 00060000
  353. [15:11:01]1150 mmu set 00070000, pos 00070000
  354. [15:11:01]1150 mmu set 00080000, pos 00080000
  355. [15:11:01]1150 mmu set 00090000, pos 00090000
  356. [15:11:01]1150 mmu set 000a0000, pos 000a0000
  357. [15:11:01]1150 mmu set 000b0000, pos 000b0000
  358. [15:11:01]1150 mmu set 000c0000, pos 000c0000
  359. [15:11:01]1150 mmu set 000d0000, pos 000d0000
  360. [15:11:01]1150 mmu set 000e0000, pos 000e0000
  361. [15:11:01]1150 mmu set 000f0000, pos 000f0000
  362. [15:11:01]1150 mmu set 00100000, pos 00100000
  363. [15:11:01]1150 mmu set 00110000, pos 00110000
  364. [15:11:01]ets Jul 29 2019 12:21:46
  365. [15:11:01]
  366. [15:11:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  367. [15:11:01]configsip: 0, SPIWP:0xee
  368. [15:11:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  369. [15:11:01]mode:DIO, clock div:1
  370. [15:11:01]load:0x3fff0018,len:4
  371. [15:11:01]load:0x7fbf005c,len:84
  372. [15:11:01]load:0x296f6e28,len:694315132
  373. [15:11:01]1150 mmu set 00010000, pos 00010000
  374. [15:11:01]1150 mmu set 00020000, pos 00020000
  375. [15:11:01]1150 mmu set 00030000, pos 00030000
  376. [15:11:01]1150 mmu set 00040000, pos 00040000
  377. [15:11:01]1150 mmu set 00050000, pos 00050000
  378. [15:11:01]1150 mmu set 00060000, pos 00060000
  379. [15:11:01]1150 mmu set 00070000, pos 00070000
  380. [15:11:01]1150 mmu set 00080000, pos 00080000
  381. [15:11:01]1150 mmu set 00090000, pos 00090000
  382. [15:11:01]1150 mmu set 000a0000, pos 000a0000
  383. [15:11:01]1150 mmu set 000b0000, pos 000b0000
  384. [15:11:01]1150 mmu set 000c0000, pos 000c0000
  385. [15:11:01]1150 mmu set 000d0000, pos 000d0000
  386. [15:11:02]1150 mmu set 000e0000, pos 000e0000
  387. [15:11:02]1150 mmu set 000f0000, pos 000f0000
  388. [15:11:02]1150 mmu set 00100000, pos 00100000
  389. [15:11:02]1150 mmu set 00110000, pos 00110000
  390. [15:11:02]ets Jul 29 2019 12:21:46
  391. [15:11:02]
  392. [15:11:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  393. [15:11:02]configsip: 0, SPIWP:0xee
  394. [15:11:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  395. [15:11:02]mode:DIO, clock div:1
  396. [15:11:02]load:0x3fff0018,len:4
  397. [15:11:02]load:0x7fbf005c,len:84
  398. [15:11:02]load:0x296b6e28,len:694315116
  399. [15:11:02]1150 mmu set 00010000, pos 00010000
  400. [15:11:02]1150 mmu set 00020000, pos 00020000
  401. [15:11:02]1150 mmu set 00030000, pos 00030000
  402. [15:11:02]1150 mmu set 00040000, pos 00040000
  403. [15:11:02]1150 mmu set 00050000, pos 00050000
  404. [15:11:02]1150 mmu set 00060000, pos 00060000
  405. [15:11:02]1150 mmu set 00070000, pos 00070000
  406. [15:11:02]1150 mmu set 00080000, pos 00080000
  407. [15:11:02]1150 mmu set 00090000, pos 00090000
  408. [15:11:02]1150 mmu set 000a0000, pos 000a0000
  409. [15:11:02]1150 mmu set 000b0000, pos 000b0000
  410. [15:11:02]1150 mmu set 000c0000, pos 000c0000
  411. [15:11:02]1150 mmu set 000d0000, pos 000d0000
  412. [15:11:02]1150 mmu set 000e0000, pos 000e0000
  413. [15:11:02]1150 mmu set 000f0000, pos 000f0000
  414. [15:11:02]1150 mmu set 00100000, pos 00100000
  415. [15:11:02]1150 mmu set 00110000, pos 00110000
  416. [15:11:02]ets Jul 29 2019 12:21:46
  417. [15:11:02]
  418. [15:11:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  419. [15:11:02]configsip: 0, SPIWP:0xee
  420. [15:11:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  421. [15:11:02]mode:DIO, clock div:1
  422. [15:11:02]load:0x3fff0018,len:4
  423. [15:11:02]load:0x7fbf005c,len:84
  424. [15:11:02]load:0x296b6e28,len:694315132
  425. [15:11:02]1150 mmu set 00010000, pos 00010000
  426. [15:11:02]1150 mmu set 00020000, pos 00020000
  427. [15:11:02]1150 mmu set 00030000, pos 00030000
  428. [15:11:02]1150 mmu set 00040000, pos 00040000
  429. [15:11:02]1150 mmu set 00050000, pos 00050000
  430. [15:11:02]1150 mmu set 00060000, pos 00060000
  431. [15:11:02]1150 mmu set 00070000, pos 00070000
  432. [15:11:02]1150 mmu set 00080000, pos 00080000
  433. [15:11:02]1150 mmu set 00090000, pos 00090000
  434. [15:11:02]1150 mmu set 000a0000, pos 000a0000
  435. [15:11:02]1150 mmu set 000b0000, pos 000b0000
  436. [15:11:02]1150 mmu set 000c0000, pos 000c0000
  437. [15:11:02]1150 mmu set 000d0000, pos 000d0000
  438. [15:11:02]1150 mmu set 000e0000, pos 000e0000
  439. [15:11:02]1150 mmu set 000f0000, pos 000f0000
  440. [15:11:02]1150 mmu set 00100000, pos 00100000
  441. [15:11:02]1150 mmu set 00110000, pos 00110000
  442. [15:11:02]ets Jul 29 2019 12:21:46
  443. [15:11:02]
  444. [15:11:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  445. [15:11:02]configsip: 0, SPIWP:0xee
  446. [15:11:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  447. [15:11:02]mode:DIO, clock div:1
  448. [15:11:02]load:0x3fff0018,len:4
  449. [15:11:02]load:0x7fbf005c,len:84
  450. [15:11:02]load:0x296b6e28,len:694315132
  451. [15:11:02]1150 mmu set 00010000, pos 00010000
  452. [15:11:02]1150 mmu set 00020000, pos 00020000
  453. [15:11:02]1150 mmu set 00030000, pos 00030000
  454. [15:11:02]1150 mmu set 00040000, pos 00040000
  455. [15:11:02]1150 mmu set 00050000, pos 00050000
  456. [15:11:02]1150 mmu set 00060000, pos 00060000
  457. [15:11:02]1150 mmu set 00070000, pos 00070000
  458. [15:11:02]1150 mmu set 00080000, pos 00080000
  459. [15:11:02]1150 mmu set 00090000, pos 00090000
  460. [15:11:03]1150 mmu set 000a0000, pos 000a0000
  461. [15:11:03]1150 mmu set 000b0000, pos 000b0000
  462. [15:11:03]1150 mmu set 000c0000, pos 000c0000
  463. [15:11:03]1150 mmu set 000d0000, pos 000d0000
  464. [15:11:03]1150 mmu set 000e0000, pos 000e0000
  465. [15:11:03]1150 mmu set 000f0000, pos 000f0000
  466. [15:11:03]1150 mmu set 00100000, pos 00100000
  467. [15:11:03]1150 mmu set 00110000, pos 00110000
  468. [15:11:03]ets Jul 29 2019 12:21:46
  469. [15:11:03]
  470. [15:11:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  471. [15:11:03]configsip: 0, SPIWP:0xee
  472. [15:11:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  473. [15:11:03]mode:DIO, clock div:1
  474. [15:11:03]load:0x3fff0018,len:4
  475. [15:11:03]load:0x7fbf005c,len:84
  476. [15:11:03]load:0x296b6e28,len:694315132
  477. [15:11:03]1150 mmu set 00010000, pos 00010000
  478. [15:11:03]1150 mmu set 00020000, pos 00020000
  479. [15:11:03]1150 mmu set 00030000, pos 00030000
  480. [15:11:03]1150 mmu set 00040000, pos 00040000
  481. [15:11:03]1150 mmu set 00050000, pos 00050000
  482. [15:11:03]1150 mmu set 00060000, pos 00060000
  483. [15:11:03]1150 mmu set 00070000, pos 00070000
  484. [15:11:03]1150 mmu set 00080000, pos 00080000
  485. [15:11:03]1150 mmu set 00090000, pos 00090000
  486. [15:11:03]1150 mmu set 000a0000, pos 000a0000
  487. [15:11:03]1150 mmu set 000b0000, pos 000b0000
  488. [15:11:03]1150 mmu set 000c0000, pos 000c0000
  489. [15:11:03]1150 mmu set 000d0000, pos 000d0000
  490. [15:11:03]1150 mmu set 000e0000, pos 000e0000
  491. [15:11:03]1150 mmu set 000f0000, pos 000f0000
  492. [15:11:03]1150 mmu set 00100000, pos 00100000
  493. [15:11:03]1150 mmu set 00110000, pos 00110000
  494. [15:11:03]ets Jul 29 2019 12:21:46
  495. [15:11:03]
  496. [15:11:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  497. [15:11:03]configsip: 0, SPIWP:0xee
  498. [15:11:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  499. [15:11:03]mode:DIO, clock div:1
  500. [15:11:03]load:0x3fff0018,len:4
  501. [15:11:03]load:0x7fbf005c,len:84
  502. [15:11:03]load:0x296b6e28,len:694315132
  503. [15:11:03]1150 mmu set 00010000, pos 00010000
  504. [15:11:03]1150 mmu set 00020000, pos 00020000
  505. [15:11:03]1150 mmu set 00030000, pos 00030000
  506. [15:11:03]1150 mmu set 00040000, pos 00040000
  507. [15:11:03]1150 mmu set 00050000, pos 00050000
  508. [15:11:03]1150 mmu set 00060000, pos 00060000
  509. [15:11:03]1150 mmu set 00070000, pos 00070000
  510. [15:11:03]1150 mmu set 00080000, pos 00080000
  511. [15:11:03]1150 mmu set 00090000, pos 00090000
  512. [15:11:03]1150 mmu set 000a0000, pos 000a0000
  513. [15:11:03]1150 mmu set 000b0000, pos 000b0000
  514. [15:11:03]1150 mmu set 000c0000, pos 000c0000
  515. [15:11:03]1150 mmu set 000d0000, pos 000d0000
  516. [15:11:03]1150 mmu set 000e0000, pos 000e0000
  517. [15:11:03]1150 mmu set 000f0000, pos 000f0000
  518. [15:11:03]1150 mmu set 00100000, pos 00100000
  519. [15:11:03]1150 mmu set 00110000, pos 00110000
  520. [15:11:03]ets Jul 29 2019 12:21:46
  521. [15:11:03]
  522. [15:11:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  523. [15:11:03]configsip: 0, SPIWP:0xee
  524. [15:11:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  525. [15:11:03]mode:DIO, clock div:1
  526. [15:11:03]load:0x3fff0018,len:4
  527. [15:11:03]load:0x7fbf005c,len:84
  528. [15:11:03]load:0x296b6e28,len:694315132
  529. [15:11:03]1150 mmu set 00010000, pos 00010000
  530. [15:11:03]1150 mmu set 00020000, pos 00020000
  531. [15:11:03]1150 mmu set 00030000, pos 00030000
  532. [15:11:03]1150 mmu set 00040000, pos 00040000
  533. [15:11:03]1150 mmu set 00050000, pos 00050000
  534. [15:11:03]1150 mmu set 00060000, pos 00060000
  535. [15:11:04]1150 mmu set 00070000, pos 00070000
  536. [15:11:04]1150 mmu set 00080000, pos 00080000
  537. [15:11:04]1150 mmu set 00090000, pos 00090000
  538. [15:11:04]1150 mmu set 000a0000, pos 000a0000
  539. [15:11:04]1150 mmu set 000b0000, pos 000b0000
  540. [15:11:04]1150 mmu set 000c0000, pos 000c0000
  541. [15:11:04]1150 mmu set 000d0000, pos 000d0000
  542. [15:11:04]1150 mmu set 000e0000, pos 000e0000
  543. [15:11:04]1150 mmu set 000f0000, pos 000f0000
  544. [15:11:04]1150 mmu set 00100000, pos 00100000
  545. [15:11:04]1150 mmu set 00110000, pos 00110000
  546. [15:11:04]ets Jul 29 2019 12:21:46
  547. [15:11:04]
  548. [15:11:04]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
  549. [15:11:04]configsip: 0, SPIWP:0xee
  550. [15:11:04]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
  551. [15:11:04]mode:DIO, clock div:1
  552. [15:11:04]load:0x3fff0018,len:4
  553. [15:11:04]load:0x7fbf005c,len:84
  554. [15:11:04]load:0x296b6e28,len:694315116
  555. [15:11:04]1150 mmu set 00010000, pos 00010000
  556. [15:11:04]1150 mmu set 00020000, pos 00020000
  557. [15:11:04]1150 mmu set 00030000, pos 00030000
  558. [15:11:04]1150 mmu set 00040000, pos 00040000
  559. [15:11:04]
  560. Serial port closed!
  561.  
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