----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.03.2019 18:44:12
-- Design Name:
-- Module Name: IF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ifSchema is
    Port(SRST : in STD_LOGIC;
        CLK : in STD_LOGIC;
        en : in STD_LOGIC;
        bAddr : in STD_LOGIC_VECTOR(15 downto 0);
        pcSRC : in STD_LOGIC;
        jAddr : in STD_LOGIC_VECTOR(15 downto 0);
        jump : in STD_LOGIC;
        instruction : out STD_LOGIC_VECTOR(15 downto 0);
        nextPc : out STD_LOGIC_VECTOR(15 downto 0));
end ifSchema;

architecture Behavioral of ifSchema is
type rom_array is array(0 to 15) of STD_LOGIC_VECTOR(15 downto 0);
signal rom : rom_array := (
B"000_000_000_001_0_001", --0011 add $1, $0, $0
B"001_000_100_0000111", --2207 addi $4, $0, 7
B"000_000_000_010_0_001", --0021 $2, $0, $0
B"000_000_000_101_0_001", --0051 $5, $0, $0
B"100_001_100_0001011", --860B $1, $4, 11
B"000_111_111_111_0_000", -- 1FF0 xor $7, $7, $7
B"010_010_011_0000000", --4980 lw $3, 0($2)
B"001_000_111_0000001", --2381 addi $7, $0, 1
B"000_011_111_111_0_000", --0FF0 xor $7, $3, $7
B"000_111_011_111_0_111", --1DF7 slt $7, $7, $3
B"110_111_000_0000010", --DC0D bgtz $7, 2
B"000_101_011_101_0_001", --15D1 add $5, $5, $3
B"001_010_010_0000001", --2901 addi $2, $2, 1
B"001_001_001_0000001", --2481 addi $1, $1, 1
B"101_0000000000100", --A004 j 4
B"011_101_000_0001010", --740A sw $5, 10($0)
others => x"9999");

signal regOut : STD_LOGIC_VECTOR(15 downto 0);
signal muxOut : STD_LOGIC_VECTOR(15 downto 0);
signal regOut_1 : STD_LOGIC_VECTOR(15 downto 0);
signal muxOut2 : STD_LOGIC_VECTOR(15 downto 0);

begin

process(clk)
begin
    if rising_edge(clk) then
        if SRST = '1' then
          regOut <= x"0000";
        elsif en ='1' then
            regOut <= muxOut;
        end if;
     end if;
end process;

regOut_1 <= regOut + 1;

nextPc <= regOut_1;

instruction <= rom(CONV_INTEGER(regOut(3 downto 0)));

process(pcSRC)
begin
    case pcSRC is
        when '0' => muxOut2 <= regOut_1;
        when '1' => muxOut2 <= bAddr;
    end case;
end process;

process(jump)
begin
    case jump is
        when '0' => muxOut <= muxOut2;
        when '1' => muxOut <= jAddr;
    end case;
end process;

end Behavioral;