module controller(clk, R1, R2, R3, Pc, P1, P2, P3, P4);
    input clk, R1, R2, R3, Pc;
    output r    P1, P2, P3, P4;

always@(negedge Pc, R1, R2, R3) begin
        if(R1)
            P1 <= 1;
        else if (R2) begin
            P1 <= 0;
            P2 <= 1;
            end
        else if (R3) begin
            P1 <= 0;
            P2 <= 0;
            P3 <= 1;
            end
        else begin
            P1 <= 0;
            P2 <= 0;
            P3 <= 0;
            P4 <= 1;
            end
    end

    always@(negedge P1, R2, R3) begin
        if(R2)
            P2 <= 1;
        else if (R3) begin
            P2 <= 0;
            P3 <= 1;
            end
        else begin
            P2 <= 0;
            P3 <= 0;
            P4 <= 1;
            end
    end

    always@(negedge P2, R3) begin
        if(R3)
            P3 <= 1;
        else begin
            P3 <= 0;
            P4 <= 1;
            end
    end

    always@(negedge P3) begin
            P4 <= 1;
    end

endmodule