library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cw2vhdl is
	Port (Ai		:	in	STD_LOGIC;
			Bi		: 	in	STD_LOGIC;
			Pwe	: 	in	STD_LOGIC;
			SW1	:	in	STD_LOGIC;
			Pwy	:	out STD_LOGIC;
			Wyn	:	out STD_LOGIC);
end cw2vhdl;

architecture Behavioral of cw2vhdl is
	begin
		Wyn <= (((not Ai) and (not Bi) and Pwe) or ((not Ai) and Bi and (not Pwe)) or(Ai and  Bi and Pwe) or (Ai and (not Bi) and (not Pwe)));

		Pwy <= ((Bi and Pwe) or (Ai and Bi) or (Ai and Pwe)) when SW1 = '0'
		else ((not Ai) and Bi or ((not Ai) and (not Pwe)) or (Bi and Pwe));
end Behavioral;