Lab9

module Lab9(
                input CLOCK_50,
                input [2:0] KEY,
                output reg [2:0] LEDR,
                output wire HEX0
);

wire M1,S1,S2;
reg [3:0] cm;
reg [2:0] state;

oneshot(KEY[0], CLOCK_50, M1);
oneshot(KEY[1], CLOCK_50, S1);
oneshot(KEY[2], CLOCK_50, S2);
hex_7seg(cm, HEX0);
parameter zero=0, one=1, two=2;

initial
begin
    state = zero;
end

always @(state)
begin
    case (state)
        zero:
        begin
            LEDR[0] = 1;
            LEDR[1] = 0;
            LEDR[2] = 0;
        end
        one:
        begin
            LEDR[0] = 0;
            LEDR[1] = 1;
            LEDR[2] = 0;
        end
        two:
        begin
            LEDR[0] = 0;
            LEDR[1] = 0;
            LEDR[2] = 1;
        end
    endcase
end

always @(*)
begin
    case(state)
        zero:
        begin
            if(M1) begin
                cm = cm+1;
                if(cm > 3) begin
                    state = one;
                    cm = 0;
                end
            end
        end
        one:
        begin
            if(S1) begin
                state = two;
            end
        end
        two:
        begin
            if(S2) begin
                state = zero;
            end
        end
    endcase

end
endmodule


module oneshot(
                    input A,
                    input clk,
                    output reg A_state);

reg [1:3] r;

always @ (posedge clk)
begin
    A_state <= r[3] & !r[2];
     r = {A , r[1:2]};
end
endmodule


module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
        4'ha: seg = 7'b0001000;
        4'hb: seg = 7'b0000011;
        4'hc: seg = 7'b1000110;
        4'hd: seg = 7'b0100001;
        4'he: seg = 7'b0000110;
        4'hf: seg = 7'b0001110;
endcase
endmodule