Lab Report 4

// file: Full Adder.v
// author: @maco

`timescale 1ns/1ns

module FullAdder(s,c,x,y,cin);
input x,y,cin;
output s,c;
assign s=x^y^cin;
wire f,g,h;
assign f=x&y;
assign g=y&cin;
assign h=x&cin;
assign c=f|g|h;
endmodule
// file: addsub.v
// author: @maco

`timescale 1ns/1ns

module addsub #(parameter N=4)(input [N-1:0] a, input [N-1:0]b, output [N:0] out);
wire [N:0] carry;
wire [N-1:0] sum;
wire [N-1:0] result;
input sub;
xor(carry[0],sub,0);

genvar i;

generate

for ( i=0; i<N;i=i+1)
begin: myblock
if(sub==0)begin
FullAdder full_inst(.s(sum[i]),.c(carry[i+1]),.x(a[i]),.y(b[i]),.cin(carry[i]));
end
else begin

FullAdder full_inst(.s(sum[i]),.c(carry[i+1]),.x(a[i]),.y(~b[i]),.cin(carry[i]));
end
end
endgenerate

wire fcarry;
xor(fcarry, carry[N],sub);
assign out ={fcarry,sum};

endmodule