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6502_CS

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  1. #cpudef "CPU_6502_CS"
  2. {
  3. #bits 8
  4.  
  5. ;------------------------------------------------------------------------------
  6. ; Add with Carry
  7. ADC #{src} -> 0x69[7:0] @ src[7:0]
  8. ADC {src} -> {assert(src <= 0xFF), 0x65[7:0] @ src[7:0]}
  9. ADC {src},X -> {assert(src <= 0xFF), 0x75[7:0] @ src[7:0]}
  10. ADC {src} -> {assert(src > 0xFF), 0x6D[7:0] @ src[7:0] @ src[15:8]}
  11. ADC {src},X -> {assert(src > 0xFF), 0x7D[7:0] @ src[7:0] @ src[15:8]}
  12. ADC {src},Y -> {assert(src > 0xFF), 0x79[7:0] @ src[7:0] @ src[15:8]}
  13. ADC ({src},X) -> 0x61[7:0] @ src[7:0]
  14. ADC ({src}),Y -> 0x71[7:0] @ src[7:0]
  15.  
  16. ;------------------------------------------------------------------------------
  17. ; Logic AND
  18. AND #{src} -> 0x29[7:0] @ src[7:0]
  19. AND {src} -> {assert(src <= 0xFF), 0x25[7:0] @ src[7:0]}
  20. AND {src},X -> {assert(src <= 0xFF), 0x35[7:0] @ src[7:0]}
  21. AND {src} -> {assert(src > 0xFF), 0x2D[7:0] @ src[7:0] @ src[15:8]}
  22. AND {src},X -> {assert(src > 0xFF), 0x3D[7:0] @ src[7:0] @ src[15:8]}
  23. AND {src},Y -> {assert(src > 0xFF), 0x39[7:0] @ src[7:0] @ src[15:8]}
  24. AND ({src},X) -> 0x21[7:0] @ src[7:0]
  25. AND ({src}),Y -> 0x31[7:0] @ src[7:0]
  26.  
  27. ;------------------------------------------------------------------------------
  28. ; Arithmetic Shift Left
  29. ASL A -> 0x0A[7:0]
  30. ASL {src} -> {assert(src <= 0xFF), 0x07[7:0] @ src[7:0]}
  31. ASL {src},X -> {assert(src <= 0xFF), 0x16[7:0] @ src[7:0]}
  32. ASL {src} -> {assert(src > 0xFF), 0x0E[7:0] @ src[7:0] @ src[15:8]}
  33. ASL {src},X -> {assert(src > 0xFF), 0x1E[7:0] @ src[7:0] @ src[15:8]}
  34.  
  35. ;------------------------------------------------------------------------------
  36. ; Branch on Carry Clear
  37. BCC {src} -> 0x90[7:0] @ (src - (pc - 2))[7:0]
  38.  
  39. ;------------------------------------------------------------------------------
  40. ; Branch on Carry Set
  41. BCS {src} -> 0xB0[7:0] @ (src - (pc - 2))[7:0]
  42.  
  43. ;------------------------------------------------------------------------------
  44. ; Branch on Equal (Zero Set)
  45. BEQ {src} -> 0xF0[7:0] @ (src - (pc - 2))[7:0]
  46.  
  47. ;------------------------------------------------------------------------------
  48. ; Bit Test
  49. BIT {src} -> {assert(src <= 0xFF), 0x24[7:0] @ src[7:0]}
  50. BIT {src} -> {assert(src > 0xFF), 0x2C[7:0] @ src[7:0] @ src[15:8]}
  51.  
  52. ;------------------------------------------------------------------------------
  53. ; Branch on Minus (Negative Set)
  54. BMI {src} -> 0x30[7:0] @ (src - (pc - 2))[7:0]
  55.  
  56. ;------------------------------------------------------------------------------
  57. ; Branch on Not Equal (Zero Clear)
  58. BNE {src} -> 0xD0[7:0] @ (src - (pc - 2))[7:0]
  59.  
  60. ;------------------------------------------------------------------------------
  61. ; Branch on Plus (Negative Clear)
  62. BPL {src} -> 0x10[7:0] @ (src - (pc - 2))[7:0]
  63.  
  64. ;------------------------------------------------------------------------------
  65. ; Break (Interrupt)
  66. BRK -> 0x00[7:0]
  67.  
  68. ;------------------------------------------------------------------------------
  69. ; Branch on Overflow Clear
  70. BVC {src} -> 0x50[7:0] @ (src - (pc - 2))[7:0]
  71.  
  72. ;------------------------------------------------------------------------------
  73. ; Branch on Overflow Set
  74. BVS {src} -> 0x70[7:0] @ (src - (pc - 2))[7:0]
  75.  
  76. ;------------------------------------------------------------------------------
  77. ; Clear Carry
  78. CLC -> 0x18[7:0]
  79.  
  80. ;------------------------------------------------------------------------------
  81. ; Clear Decimal
  82. CLD -> 0xD8[7:0]
  83.  
  84. ;------------------------------------------------------------------------------
  85. ; Clear Interrupt Disable
  86. CLI -> 0x58[7:0]
  87.  
  88. ;------------------------------------------------------------------------------
  89. ; Clear Overflow
  90. CLV -> 0xB8[7:0]
  91.  
  92. ;------------------------------------------------------------------------------
  93. ; Compare with Accumulator
  94. CMP #{src} -> 0xC9[7:0] @ src[7:0]
  95. CMP {src} -> {assert(src <= 0xFF), 0xC5[7:0] @ src[7:0]}
  96. CMP {src},X -> {assert(src <= 0xFF), 0xD5[7:0] @ src[7:0]}
  97. CMP {src} -> {assert(src > 0xFF), 0xCD[7:0] @ src[7:0] @ src[15:8]}
  98. CMP {src},X -> {assert(src > 0xFF), 0xDD[7:0] @ src[7:0] @ src[15:8]}
  99. CMP {src},Y -> {assert(src > 0xFF), 0xD9[7:0] @ src[7:0] @ src[15:8]}
  100. CMP ({src},X) -> 0xC1[7:0] @ src[7:0]
  101. CMP ({src}),Y -> 0xD1[7:0] @ src[7:0]
  102.  
  103. ;------------------------------------------------------------------------------
  104. ; Compare with X
  105. CPX #{src} -> 0xE0[7:0] @ src[7:0]
  106. CPX {src} -> {assert(src <= 0xFF), 0xE4[7:0] @ src[7:0]}
  107. CPX {src} -> {assert(src > 0xFF), 0xEC[7:0] @ src[7:0] @ src[15:8]}
  108.  
  109. ;------------------------------------------------------------------------------
  110. ; Compare with Y
  111. CPY #{src} -> 0xC0[7:0] @ src[7:0]
  112. CPY {src} -> {assert(src <= 0xFF), 0xC4[7:0] @ src[7:0]}
  113. CPY {src} -> {assert(src > 0xFF), 0xCC[7:0] @ src[7:0] @ src[15:8]}
  114.  
  115. ;------------------------------------------------------------------------------
  116. ; Decrement
  117. DEC {src} -> {assert(src <= 0xFF), 0xC6[7:0] @ src[7:0]}
  118. DEC {src},X -> {assert(src <= 0xFF), 0xD6[7:0] @ src[7:0]}
  119. DEC {src} -> {assert(src > 0xFF), 0xCE[7:0] @ src[7:0] @ src[15:8]}
  120. DEC {src},X -> {assert(src > 0xFF), 0xDE[7:0] @ src[7:0] @ src[15:8]}
  121.  
  122. ;------------------------------------------------------------------------------
  123. ; Decrement X
  124. DEX -> 0xCA[7:0]
  125.  
  126. ;------------------------------------------------------------------------------
  127. ; Decrement Y
  128. DEY -> 0x88[7:0]
  129.  
  130. ;------------------------------------------------------------------------------
  131. ; Logic XOR
  132. EOR #{src} -> 0x49[7:0] @ src[7:0]
  133. EOR {src} -> {assert(src <= 0xFF), 0x45[7:0] @ src[7:0]}
  134. EOR {src},X -> {assert(src <= 0xFF), 0x55[7:0] @ src[7:0]}
  135. EOR {src} -> {assert(src > 0xFF), 0x4D[7:0] @ src[7:0] @ src[15:8]}
  136. EOR {src},X -> {assert(src > 0xFF), 0x5D[7:0] @ src[7:0] @ src[15:8]}
  137. EOR {src},Y -> {assert(src > 0xFF), 0x59[7:0] @ src[7:0] @ src[15:8]}
  138. EOR ({src},X) -> 0x41[7:0] @ src[7:0]
  139. EOR ({src}),Y -> 0x51[7:0] @ src[7:0]
  140.  
  141. ;------------------------------------------------------------------------------
  142. ; Increment
  143. INC {src} -> {assert(src <= 0xFF), 0xE6[7:0] @ src[7:0]}
  144. INC {src},X -> {assert(src <= 0xFF), 0xF6[7:0] @ src[7:0]}
  145. INC {src} -> {assert(src > 0xFF), 0xEE[7:0] @ src[7:0] @ src[15:8]}
  146. INC {src},X -> {assert(src > 0xFF), 0xFE[7:0] @ src[7:0] @ src[15:8]}
  147.  
  148. ;------------------------------------------------------------------------------
  149. ; Increment X
  150. INX -> 0xE8[7:0]
  151.  
  152. ;------------------------------------------------------------------------------
  153. ; Increment Y
  154. INY -> 0xC8[7:0]
  155.  
  156. ;------------------------------------------------------------------------------
  157. ; Jump
  158. JMP {src} -> 0x4C[7:0] @ src[7:0] @ src[15:8]
  159. JMP ind -> 0x6C[7:0] @ src[7:0] @ src[15:8]
  160.  
  161. ;------------------------------------------------------------------------------
  162. ; Jump Subroutine
  163. JSR {src} -> 0x20[7:0] @ src[7:0] @ src[15:8]
  164.  
  165. ;------------------------------------------------------------------------------
  166. ; Load Accumulator
  167. LDA #{src} -> 0xA9[7:0] @ src[7:0]
  168. LDA {src} -> {assert(src <= 0xFF), 0xA5[7:0] @ src[7:0]}
  169. LDA {src},X -> {assert(src <= 0xFF), 0xB5[7:0] @ src[7:0]}
  170. LDA {src} -> {assert(src > 0xFF), 0xAD[7:0] @ src[7:0] @ src[15:8]}
  171. LDA {src},X -> {assert(src > 0xFF), 0xBD[7:0] @ src[7:0] @ src[15:8]}
  172. LDA {src},Y -> {assert(src > 0xFF), 0xB9[7:0] @ src[7:0] @ src[15:8]}
  173. LDA ({src},X) -> 0xA1[7:0] @ src[7:0]
  174. LDA ({src}),Y -> 0xB1[7:0] @ src[7:0]
  175.  
  176. ;------------------------------------------------------------------------------
  177. ; Load X
  178. LDX #{src} -> 0xA2[7:0] @ src[7:0]
  179. LDX {src} -> {assert(src <= 0xFF), 0xA6[7:0] @ src[7:0]}
  180. LDX {src},Y -> {assert(src <= 0xFF), 0xB6[7:0] @ src[7:0]}
  181. LDX {src} -> {assert(src > 0xFF), 0xAE[7:0] @ src[7:0] @ src[15:8]}
  182. LDX {src},Y -> {assert(src > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  183.  
  184. ;------------------------------------------------------------------------------
  185. ; Load Y
  186. LDY #{src} -> 0xA0[7:0] @ src[7:0]
  187. LDY {src} -> {assert(src <= 0xFF), 0xA4[7:0] @ src[7:0]}
  188. LDY {src},X -> {assert(src <= 0xFF), 0xB4[7:0] @ src[7:0]}
  189. LDY {src} -> {assert(src > 0xFF), 0xAC[7:0] @ src[7:0] @ src[15:8]}
  190. LDY {src},X -> {assert(src > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  191.  
  192. ;------------------------------------------------------------------------------
  193. ; Logical Shift Right
  194. LSR A -> 0x4A[7:0]
  195. LSR {src} -> {assert(src <= 0xFF), 0x46[7:0] @ src[7:0]}
  196. LSR {src},X -> {assert(src <= 0xFF), 0x56[7:0] @ src[7:0]}
  197. LSR {src} -> {assert(src > 0xFF), 0x4E[7:0] @ src[7:0] @ src[15:8]}
  198. LSR {src},X -> {assert(src > 0xFF), 0x5E[7:0] @ src[7:0] @ src[15:8]}
  199.  
  200. ;------------------------------------------------------------------------------
  201. ; No Operation
  202. NOP -> 0xEA[7:0]
  203.  
  204. ;------------------------------------------------------------------------------
  205. ; Logic OR
  206. ORA #{src} -> 0x09[7:0] @ src[7:0]
  207. ORA {src} -> {assert(src <= 0xFF), 0x06[7:0] @ src[7:0]}
  208. ORA {src},X -> {assert(src <= 0xFF), 0x15[7:0] @ src[7:0]}
  209. ORA {src} -> {assert(src > 0xFF), 0x0D[7:0] @ src[7:0] @ src[15:8]}
  210. ORA {src},X -> {assert(src > 0xFF), 0x1D[7:0] @ src[7:0] @ src[15:8]}
  211. ORA {src},Y -> {assert(src > 0xFF), 0x19[7:0] @ src[7:0] @ src[15:8]}
  212. ORA ({src},X) -> 0x01[7:0] @ src[7:0]
  213. ORA ({src}),Y -> 0x11[7:0] @ src[7:0]
  214.  
  215. ;------------------------------------------------------------------------------
  216. ; Push Accumulator
  217. PHA -> 0x48[7:0]
  218.  
  219. ;------------------------------------------------------------------------------
  220. ; Push Processor Status
  221. PHP -> 0x08[7:0]
  222.  
  223. ;------------------------------------------------------------------------------
  224. ; Pull Accumulator
  225. PLA -> 0x68[7:0]
  226.  
  227. ;------------------------------------------------------------------------------
  228. ; Pull Processor Status
  229. PLP -> 0x28[7:0]
  230.  
  231. ;------------------------------------------------------------------------------
  232. ; Rotate Left
  233. ROL A -> 0x2A[7:0]
  234. ROL {src} -> {assert(src <= 0xFF), 0x26[7:0] @ src[7:0]}
  235. ROL {src},X -> {assert(src <= 0xFF), 0x36[7:0] @ src[7:0]}
  236. ROL {src} -> {assert(src > 0xFF), 0x2E[7:0] @ src[7:0] @ src[15:8]}
  237. ROL {src},X -> {assert(src > 0xFF), 0x3E[7:0] @ src[7:0] @ src[15:8]}
  238.  
  239. ;------------------------------------------------------------------------------
  240. ; Rotate Right
  241. ROR A -> 0x6A[7:0]
  242. ROR {src} -> {assert(src <= 0xFF), 0x66[7:0] @ src[7:0]}
  243. ROR {src},X -> {assert(src <= 0xFF), 0x76[7:0] @ src[7:0]}
  244. ROR {src} -> {assert(src > 0xFF), 0x6E[7:0] @ src[7:0] @ src[15:8]}
  245. ROR {src},X -> {assert(src > 0xFF), 0x7E[7:0] @ src[7:0] @ src[15:8]}
  246.  
  247. ;------------------------------------------------------------------------------
  248. ; Return from Interrupt
  249. RTI -> 0x40[7:0]
  250.  
  251. ;------------------------------------------------------------------------------
  252. ; Return from Subroutine
  253. RTS -> 0x60[7:0]
  254.  
  255. ;------------------------------------------------------------------------------
  256. ; Subtract with Carry
  257. SBC #{src} -> 0xE9[7:0] @ src[7:0]
  258. SBC {src} -> {assert(src <= 0xFF), 0xE5[7:0] @ src[7:0]}
  259. SBC {src},X -> {assert(src <= 0xFF), 0xF5[7:0] @ src[7:0]}
  260. SBC {src} -> {assert(src > 0xFF), 0xED[7:0] @ src[7:0] @ src[15:8]}
  261. SBC {src},X -> {assert(src > 0xFF), 0xFD[7:0] @ src[7:0] @ src[15:8]}
  262. SBC {src},Y -> {assert(src > 0xFF), 0xF9[7:0] @ src[7:0] @ src[15:8]}
  263. SBC ({src},X) -> 0xE1[7:0] @ src[7:0]
  264. SBC ({src}),Y -> 0xF1[7:0] @ src[7:0]
  265.  
  266. ;------------------------------------------------------------------------------
  267. ; Set Carry
  268. SEC -> 0x38[7:0]
  269.  
  270. ;------------------------------------------------------------------------------
  271. ; Set Decimal
  272. SED -> 0xF8[7:0]
  273.  
  274. ;------------------------------------------------------------------------------
  275. ; Set Interrupt Disable
  276. SEI -> 0x78[7:0]
  277.  
  278. ;------------------------------------------------------------------------------
  279. ; Store Accumulator
  280. STA {src} -> {assert(src <= 0xFF), 0x85[7:0] @ src[7:0]}
  281. STA {src},X -> {assert(src <= 0xFF), 0x95[7:0] @ src[7:0]}
  282. STA {src} -> {assert(src > 0xFF), 0x8D[7:0] @ src[7:0] @ src[15:8]}
  283. STA {src},X -> {assert(src > 0xFF), 0x9D[7:0] @ src[7:0] @ src[15:8]}
  284. STA {src},Y -> {assert(src > 0xFF), 0x99[7:0] @ src[7:0] @ src[15:8]}
  285. STA ({src},X) -> 0x81[7:0] @ src[7:0]
  286. STA ({src}),Y -> 0x91[7:0] @ src[7:0]
  287.  
  288. ;------------------------------------------------------------------------------
  289. ; Store X
  290. STX {src} -> {assert(src <= 0xFF), 0x86[7:0] @ src[7:0]}
  291. STX {src},Y -> {assert(src <= 0xFF), 0x96[7:0] @ src[7:0]}
  292. STX {src} -> {assert(src > 0xFF), 0x8E[7:0] @ src[7:0] @ src[15:8]}
  293.  
  294. ;------------------------------------------------------------------------------
  295. ; Store Y
  296. STY {src} -> {assert(src <= 0xFF), 0x84[7:0] @ src[7:0]}
  297. STY {src},X -> {assert(src <= 0xFF), 0x94[7:0] @ src[7:0]}
  298. STY {src} -> {assert(src > 0xFF), 0x8C[7:0] @ src[7:0] @ src[15:8]}
  299.  
  300. ;------------------------------------------------------------------------------
  301. ; Transfer Accumulator to X
  302. TAX -> 0xAA[7:0]
  303.  
  304. ;------------------------------------------------------------------------------
  305. ; Transfer Accumulator to Y
  306. TAY -> 0xA8[7:0]
  307.  
  308. ;------------------------------------------------------------------------------
  309. ; Transfer Stack Pointer to X
  310. TSX -> 0xBA[7:0]
  311.  
  312. ;------------------------------------------------------------------------------
  313. ; Transfer X to Accumulator
  314. TXA -> 0x8A[7:0]
  315.  
  316. ;------------------------------------------------------------------------------
  317. ; Transfer X to Stack Pointer
  318. TXS -> 0x9A[7:0]
  319.  
  320. ;------------------------------------------------------------------------------
  321. ; Transfer Y to Accumulator
  322. TYA -> 0x98[7:0]
  323.  
  324. }
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