Guest User

Untitled

a guest
Jan 27th, 2017
517
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1.  
  2. library IEEE;
  3. use IEEE.std_logic_1164.ALL;
  4. use IEEE.numeric_std.all;
  5.  
  6. library unisim;
  7. use unisim.vcomponents.all;
  8.  
  9. entity diffclock2 is
  10.  
  11. Port (
  12. pad_p : in std_logic; -- differential pin p from sensor
  13. pad_n : in std_logic; -- differential pin n from sensor
  14. DLY_CLK : in std_logic; -- not sure what kind of clock to supply here
  15. dly_cnt : in std_logic_vector(4 downto 0); -- delay value from 0 to 31
  16. dly_ld_clk : in std_logic; -- tells IDELAYE2 to load value in dly_cnt as the new delay value
  17. dly_reset : in std_logic;
  18. dly_refclk : in std_logic; -- 200mhz clock
  19. CLK_OUT : out std_logic -- output delayed clock
  20. );
  21.  
  22. end diffclock2;
  23.  
  24.  
  25. architecture behavioral of diffclock2 is
  26.  
  27. signal CLK_IBUFG : std_logic;
  28. signal CLK_DLY : std_logic;
  29. signal CLK_BUFR : std_logic;
  30.  
  31. begin
  32.  
  33. clk_ibufg_I: IBUFGDS -- ** converts differential pin pair into single clock pin **
  34.  
  35. generic map (
  36. IOSTANDARD => "LVDS_25",
  37. DIFF_TERM => true
  38. )
  39.  
  40. port map (
  41. I => pad_p,
  42. IB => pad_n,
  43. O => CLK_IBUFG
  44. );
  45.  
  46. clk_idelay_I: IDELAYE2
  47. generic map (
  48. CINVCTRL_SEL => "FALSE",
  49. DELAY_SRC => "IDATAIN",
  50. HIGH_PERFORMANCE_MODE => "FALSE",
  51. IDELAY_TYPE => "VAR_LOAD",
  52. IDELAY_VALUE => 0,
  53. PIPE_SEL => "FALSE",
  54. REFCLK_FREQUENCY => 200.0,
  55. SIGNAL_PATTERN => "CLOCK"
  56. )
  57. port map (
  58. CNTVALUEOUT => open,
  59. DATAOUT => CLK_DLY, -- delayed clock
  60. C => DLY_CLK,
  61. CE => '0',
  62. CINVCTRL => '0',
  63. CNTVALUEIN => dly_cnt,
  64. DATAIN => '0',
  65. IDATAIN => CLK_IBUFG, -- input clock from differential pins on sensor
  66. INC => '0',
  67. LD => dly_ld_clk,
  68. LDPIPEEN => '0',
  69. REGRST => dly_reset
  70. );
  71.  
  72. csi_CLK_BUFR: BUFR -- not sure why i need this
  73. generic map (
  74. BUFR_DIVIDE => "BYPASS",
  75. SIM_DEVICE => "7SERIES"
  76. )
  77. port map (
  78. O => CLK_BUFR,
  79. CE => '1',
  80. CLR => '0',
  81. I => CLK_DLY
  82. );
  83.  
  84. -- ** i think i need DDR in here somewhere too?? **
  85.  
  86. CLK_OUT <= CLK_BUFR;
  87.  
  88. idelayctrl_I: IDELAYCTRL
  89. port map (
  90. RDY => open,
  91. REFCLK => dly_refclk, --200mhz input clock
  92. RST => dly_reset
  93. );
  94.  
  95. end behavioral;
RAW Paste Data