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BigEvilCorporation init.asm

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Jan 9th, 2018
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  1. ; ******************************************************************
  2. ; Sega Megadrive ROM header
  3. ; ******************************************************************
  4.  dc.l   0x00FFE000      ; Initial stack pointer value
  5.  dc.l   EntryPoint      ; Start of program
  6.  dc.l   Exception       ; Bus error
  7.  dc.l   Exception       ; Address error
  8.  dc.l   Exception       ; Illegal instruction
  9.  dc.l   Exception       ; Division by zero
  10.  dc.l   Exception       ; CHK exception
  11.  dc.l   Exception       ; TRAPV exception
  12.  dc.l   Exception       ; Privilege violation
  13.  dc.l   Exception       ; TRACE exception
  14.  dc.l   Exception       ; Line-A emulator
  15.  dc.l   Exception       ; Line-F emulator
  16.  dc.l   Exception       ; Unused (reserved)
  17.  dc.l   Exception       ; Unused (reserved)
  18.  dc.l   Exception       ; Unused (reserved)
  19.  dc.l   Exception       ; Unused (reserved)
  20.  dc.l   Exception       ; Unused (reserved)
  21.  dc.l   Exception       ; Unused (reserved)
  22.  dc.l   Exception       ; Unused (reserved)
  23.  dc.l   Exception       ; Unused (reserved)
  24.  dc.l   Exception       ; Unused (reserved)
  25.  dc.l   Exception       ; Unused (reserved)
  26.  dc.l   Exception       ; Unused (reserved)
  27.  dc.l   Exception       ; Unused (reserved)
  28.  dc.l   Exception       ; Spurious exception
  29.  dc.l   Exception       ; IRQ level 1
  30.  dc.l   Exception       ; IRQ level 2
  31.  dc.l   Exception       ; IRQ level 3
  32.  dc.l   HBlankInterrupt ; IRQ level 4 (horizontal retrace interrupt)
  33.  dc.l   Exception       ; IRQ level 5
  34.  dc.l   VBlankInterrupt ; IRQ level 6 (vertical retrace interrupt)
  35.  dc.l   Exception       ; IRQ level 7
  36.  dc.l   Exception       ; TRAP #00 exception
  37.  dc.l   Exception       ; TRAP #01 exception
  38.  dc.l   Exception       ; TRAP #02 exception
  39.  dc.l   Exception       ; TRAP #03 exception
  40.  dc.l   Exception       ; TRAP #04 exception
  41.  dc.l   Exception       ; TRAP #05 exception
  42.  dc.l   Exception       ; TRAP #06 exception
  43.  dc.l   Exception       ; TRAP #07 exception
  44.  dc.l   Exception       ; TRAP #08 exception
  45.  dc.l   Exception       ; TRAP #09 exception
  46.  dc.l   Exception       ; TRAP #10 exception
  47.  dc.l   Exception       ; TRAP #11 exception
  48.  dc.l   Exception       ; TRAP #12 exception
  49.  dc.l   Exception       ; TRAP #13 exception
  50.  dc.l   Exception       ; TRAP #14 exception
  51.  dc.l   Exception       ; TRAP #15 exception
  52.  dc.l   Exception       ; Unused (reserved)
  53.  dc.l   Exception       ; Unused (reserved)
  54.  dc.l   Exception       ; Unused (reserved)
  55.  dc.l   Exception       ; Unused (reserved)
  56.  dc.l   Exception       ; Unused (reserved)
  57.  dc.l   Exception       ; Unused (reserved)
  58.  dc.l   Exception       ; Unused (reserved)
  59.  dc.l   Exception       ; Unused (reserved)
  60.  dc.l   Exception       ; Unused (reserved)
  61.  dc.l   Exception       ; Unused (reserved)
  62.  dc.l   Exception       ; Unused (reserved)
  63.  dc.l   Exception       ; Unused (reserved)
  64.  dc.l   Exception       ; Unused (reserved)
  65.  dc.l   Exception       ; Unused (reserved)
  66.  dc.l   Exception       ; Unused (reserved)
  67.  dc.l   Exception       ; Unused (reserved)
  68.  dc.b "SEGA GENESIS    "                                 ; Console name
  69.  dc.b "(C)SEGA 1992.SEP"                                 ; Copyrght holder and release date
  70.  dc.b "YOUR GAME HERE                                  " ; Domestic name
  71.  dc.b "YOUR GAME HERE                                  " ; International name
  72.  dc.b "GM XXXXXXXX-XX"                                   ; Version number
  73.  dc.w 0x0000                                             ; Checksum
  74.  dc.b "J               "                                 ; I/O support
  75.  dc.l 0x00000000                                         ; Start address of ROM
  76.  dc.l __end                                              ; End address of ROM
  77.  dc.l 0x00FF0000                                         ; Start address of RAM
  78.  dc.l 0x00FFFFFF                                         ; End address of RAM
  79.  dc.l 0x00000000                                         ; SRAM enabled
  80.  dc.l 0x00000000                                         ; Unused
  81.  dc.l 0x00000000                                         ; Start address of SRAM
  82.  dc.l 0x00000000                                         ; End address of SRAM
  83.  dc.l 0x00000000                                         ; Unused
  84.  dc.l 0x00000000                                         ; Unused
  85.  dc.b "                                        "         ; Notes (unused)
  86.  dc.b "JUE             "                                 ; Country codes
  87. EntryPoint:        ; Entry point address set in ROM header
  88.  tst.w 0x00A10008  ; Test mystery reset (expansion port reset?)
  89.  bne Main          ; Branch if Not Equal (to zero) - to Main
  90.  tst.w 0x00A1000C  ; Test reset button
  91.  bne Main          ; Branch if Not Equal (to zero) - to Main
  92. HBlankInterrupt:
  93. VBlankInterrupt:
  94.  rte   ; Return from Exception
  95. Exception:
  96.  rte   ; Return from Exception
  97. Loop:
  98.  move.l #0xF, d0 ; Move 15 into register d0
  99.  move.l d0, d1   ; Move contents of register d0 into d1
  100.  jmp Loop        ; Jump back up to 'Loop'
  101.  move.l #0x00000000, d0     ; Place a 0 into d0, ready to copy to each longword of RAM
  102.  move.l #0x00000000, a0     ; Starting from address 0x0, clearing backwards
  103.  move.l #0x00003FFF, d1     ; Clearing 64k's worth of longwords (minus 1, for the loop to be correct)
  104. @Clear:
  105.  move.l d0, -(a0)           ; Decrement the address by 1 longword, before moving the zero from d0 to it
  106.  dbra d1, @Clear            ; Decrement d0, repeat until depleted
  107. ;TMSS
  108.  move.b 0x00A10001, d0      ; Move Megadrive hardware version to d0
  109.  andi.b #0x0F, d0           ; The version is stored in last four bits, so mask it with 0F
  110.  beq @Skip                  ; If version is equal to 0, skip TMSS signature
  111.  move.l #'SEGA', 0x00A14000 ; Move the string "SEGA" to 0xA14000
  112. @Skip:
  113. ;Z80_Init()
  114.  move.w #0x0100, 0x00A11100 ; Request access to the Z80 bus, by writing 0x0100 into the BUSREQ port
  115.  move.w #0x0100, 0x00A11200 ; Hold the Z80 in a reset state, by writing 0x0100 into the RESET port
  116. @Wait:
  117.  btst #0x0, 0x00A11100   ; Test bit 0 of A11100 to see if the 68k has access to the Z80 bus yet
  118.  bne @Wait               ; If we don't yet have control, branch back up to Wait
  119.  move.l #Z80Data, a0      ; Load address of data into a0
  120.  move.l #0x00A00000, a1   ; Copy Z80 RAM address to a1
  121.  move.l #0x29, d0         ; 42 bytes of init data (minus 1 for counter)
  122. @Copy:
  123.  move.b (a0)+, (a1)+      ; Copy data, and increment the source/dest addresses
  124.  dbra d0, @Copy
  125.  move.w #0x0000, 0x00A11200 ; Release reset state
  126.  move.w #0x0000, 0x00A11100 ; Release control of bus
  127. Z80Data:
  128.  dc.w 0xaf01, 0xd91f
  129.  dc.w 0x1127, 0x0021
  130.  dc.w 0x2600, 0xf977
  131.  dc.w 0xedb0, 0xdde1
  132.  dc.w 0xfde1, 0xed47
  133.  dc.w 0xed4f, 0xd1e1
  134.  dc.w 0xf108, 0xd9c1
  135.  dc.w 0xd1e1, 0xf1f9
  136.  dc.w 0xf3ed, 0x5636
  137.  dc.w 0xe9e9, 0x8104
  138.  dc.w 0x8f01
  139. ;PSG_Init()
  140.  move.l #PSGData, a0      ; Load address of PSG data into a0
  141.  move.l #0x03, d0         ; 4 bytes of data
  142. @Copy:
  143.  move.b (a0)+, 0x00C00011 ; Copy data to PSG RAM
  144.  dbra d0, @Copy
  145. PSGData:
  146.  dc.w 0x9fbf, 0xdfff
  147. ;VDP_Init()
  148.  move.l #VDPRegisters, a0 ; Load address of register table into a0
  149.  move.l #0x18, d0         ; 24 registers to write
  150.  move.l #0x00008000, d1   ; 'Set register 0' command (and clear the rest of d1 ready)
  151. @Copy:
  152.  move.b (a0)+, d1         ; Move register value to lower byte of d1
  153.  move.w d1, 0x00C00004    ; Write command and value to VDP control port
  154.  add.w #0x0100, d1        ; Increment register #
  155.  dbra d0, @Copy
  156. VDPRegisters:
  157.  dc.b 0x20 ; 0: Horiz. interrupt on, plus bit 2 (unknown, but docs say it needs to be on)
  158.  dc.b 0x74 ; 1: Vert. interrupt on, display on, DMA on, V28 mode (28 cells vertically), + bit 2
  159.  dc.b 0x30 ; 2: Pattern table for Scroll Plane A at 0xC000 (bits 3-5)
  160.  dc.b 0x40 ; 3: Pattern table for Window Plane at 0x10000 (bits 1-5)
  161.  dc.b 0x05 ; 4: Pattern table for Scroll Plane B at 0xA000 (bits 0-2)
  162.  dc.b 0x70 ; 5: Sprite table at 0xE000 (bits 0-6)
  163.  dc.b 0x00 ; 6: Unused
  164.  dc.b 0x00 ; 7: Background colour - bits 0-3 = colour, bits 4-5 = palette
  165.  dc.b 0x00 ; 8: Unused
  166.  dc.b 0x00 ; 9: Unused
  167.  dc.b 0x00 ; 10: Frequency of Horiz. interrupt in Rasters (number of lines travelled by the beam)
  168.  dc.b 0x08 ; 11: External interrupts on, V/H scrolling on
  169.  dc.b 0x81 ; 12: Shadows and highlights off, interlace off, H40 mode (40 cells horizontally)
  170.  dc.b 0x34 ; 13: Horiz. scroll table at 0xD000 (bits 0-5)
  171.  dc.b 0x00 ; 14: Unused
  172.  dc.b 0x00 ; 15: Autoincrement off
  173.  dc.b 0x01 ; 16: Vert. scroll 32, Horiz. scroll 64
  174.  dc.b 0x00 ; 17: Window Plane X pos 0 left (pos in bits 0-4, left/right in bit 7)
  175.  dc.b 0x00 ; 18: Window Plane Y pos 0 up (pos in bits 0-4, up/down in bit 7)
  176.  dc.b 0x00 ; 19: DMA length lo byte
  177.  dc.b 0x00 ; 20: DMA length hi byte
  178.  dc.b 0x00 ; 21: DMA source address lo byte
  179.  dc.b 0x00 ; 22: DMA source address mid byte
  180.  dc.b 0x00 ; 23: DMA source address hi byte, memory-to-VRAM mode (bits 6-7)
  181. ; Set IN I/O direction, interrupts off, on all ports
  182.  move.b #0x00, 0x000A10009 ; Controller port 1 CTRL
  183.  move.b #0x00, 0x000A1000B ; Controller port 2 CTRL
  184.  move.b #0x00, 0x000A1000D ; EXP port CTRL
  185.  move.l #0x00000000, a0    ; Move 0x0 to a0
  186.  movem.l (a0), d0-d7/a1-a7 ; Multiple move 0 to all registers
  187. ; Init status register (no trace, A7 is Interrupt Stack Pointer, no interrupts, clear condition code bits)
  188.  move #0x2700, sr
  189. Main:
  190. ; Here goes your game code
  191.  jmp __main ; Jump to the game code!
  192. __end    ; Very last line, end of ROM address
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