relu_tb.v

`include "relu.v"
`timescale 1us/1us
module tf_tb;

   // parameters
   parameter WIDTH= 4;
   parameter maxvalue = 2**(WIDTH-1)-1; // for one attribute
   parameter minvalue = -(2**(WIDTH-1)); // for one attribute

   // on testbenches, inputs are regs
   reg signed [WIDTH-1:0] in1;
   reg clk;

   // on testbenches, outputs are wires
   wire signed [WIDTH-1:0] out;

   //mac MAC1(in1,in2,clk, reset, out);

   relu #(.WIDTH(WIDTH))  TF1 (in1,out);

   initial begin
      clk = 0;     in1 = minvalue;
      #(2*2**WIDTH) $finish;

   end // initial begin

   always  #1 clk = ~clk;
   always  #2 in1 = in1+1;

   initial begin
      $monitor ("%t | in1 = %d | clk = %d | out = %d", $time, in1, clk, out);
      $dumpfile("dump.vcd");
      $dumpvars();
   end
endmodule // sr_tb