module CONTROL_MASKING(
    // Глобальная тактовая частота и ресет
    clk,
    reset_n,

    // линии шины avalone-mm slave
    mm_chipselect,
    mm_read,
    mm_write,
    mm_readdata,
    mm_writedata,
    mm_address,

    // сигналы линии синхронизации потока данных маскирования
    sink_data_mask,
    sink_valid,
    sink_ready,
    sink_sop,
    sink_eop,

    // выходной поток сигналов синхронизации и данных маскирования
    source_data_masking,
    source_valid,
    source_ready,
    source_sop,
    source_eop,

    // канал связи с контроллером i2c master
    clk50,
    vcm_i2c_scl,
    vcm_i2c_sda

);


// global clock & reset
input   clk;
input   reset_n;

// mm slave
input                           mm_chipselect;
input                           mm_read;
input                           mm_write;
output  reg [31:0]              mm_readdata;
input   [31:0]                  mm_writedata;
input   [3:0]                   mm_address;


// streaming sink
input   [23:0]                 sink_data_mask;
input                          sink_valid;
output                         sink_ready;
input                          sink_sop;
input                          sink_eop;

// streaming  data masking
output  [23:0]                 source_data_masking;
output                         source_valid;
input                          source_ready;
output                         source_sop;
output                         source_eop;

// conduit export
input                         clk50;
inout                         vcm_i2c_scl;
inout                         vcm_i2c_sda;

//////////////////////////////////////////////
parameter    VIDEO_W   = 1920, // masking area
             VIDEO_H   = 1080;

localparam   MASKING_MODE     = 1'b0,
             DEMASKING__MODE   = 1'b1;

localparam  st1 = 3'b01,
            st2 = 3'b10;
localparam base = 4'b1111;
initial begin
    state = st1;
end


reg process_start ;
reg masking_mode;

reg  [11:0]  masking_active_w ;
reg  [11:0]  masking_active_h ;
reg  [11:0]  masking_active_x_start ;
reg  [11:0]  masking_active_y_start ;

reg  [11:0]  x_cnt ;
reg  [11:0]  y_cnt ;
reg  [7:0]   smsk;
reg  [7:0]   smsk_f;
reg  [7:0]   th;

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
wire [23:0] poly =  24'h800a23;
reg [23:0] myreg;
wire [23:0] feedback;
wire [23:0] out;
wire [23:0] demask;
assign feedback = {23{myreg[23]}} & poly;
assign  out = {sink_data_mask[23:16]^myreg[23:16], sink_data_mask[15:8]^myreg[15:8], sink_data_mask[7:0]^myreg[7:0]};
assign  demask = (masking_mode)? res^(~myreg[23:0]):24'hFF_FF_FF;
reg run_musk;
reg run_nmusk;
reg run_musk_and_real;
wire [23:0] musk_data;

reg [23:0]  da      [0:16];
reg [23:0]  d       [0:16];
reg [1:0]   state;
reg [23:0]  res;
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////

assign source_data_masking  =  ((run_musk & masking_window_area)|(run_musk_and_real & masking_window_area_musk)|(run_nmusk & masking_window_area_nmusk))?
                                                                                                                (run_nmusk& masking_window_area_nmusk)?
                                                                                                                            demask
                                                                                                                            :res
                                                                                                                :sink_data_mask;

assign source_valid =  sink_valid;
assign sink_ready   =  source_ready;
assign source_sop   =  sink_sop;
assign source_eop   =  sink_eop;



///////////////////////////////////////////////////////
/// команды управления от шины avalone-mm master  /////
///////////////////////////////////////////////////////

// write
`define REG_GO              0
`define REG_CTRL            1
`define REG_MASKING_W       2
`define REG_MASKING_H       3
`define REG_MASKING_X_START 4
`define REG_MASKING_Y_START 5
`define REG_SMSK            6

`define REG_TH              7
`define MASK                8
`define nMASK               9

// read
`define REG_STATUS         0
//`define REG_SUM            1


// mm mater write
always @ (posedge clk)
begin
    if (~reset_n)
    begin
        process_start <= 1'b0;
        masking_mode    <=  MASKING_MODE;

        masking_active_w       <= 12'd200;
        masking_active_h       <= 12'd120;
        masking_active_x_start <= 12'd300;
        masking_active_y_start <= 12'd180;

        smsk                 <= 8'd10;
        smsk_f               <= 8'd1;

        th                   <= 8'd5;
    end
    else begin
      if(mm_chipselect & mm_write) begin
           if      (mm_address == `REG_GO)  process_start <= mm_writedata[0];
          else if (mm_address == `REG_CTRL) run_musk      <= mm_writedata[0];// DEMASKING__MODE
          else if (mm_address == `REG_MASKING_W)       masking_active_w       <= mm_writedata[11:0];
          else if (mm_address == `REG_MASKING_H)       masking_active_h       <= mm_writedata[11:0];
          else if (mm_address == `REG_MASKING_X_START) masking_active_x_start <= mm_writedata[11:0];
          else if (mm_address == `REG_MASKING_Y_START) masking_active_y_start <= mm_writedata[11:0];
          else if (mm_address == `REG_SMSK)    begin smsk                 <= mm_writedata[15:8];
                                                   smsk_f               <= mm_writedata[7:0];
                                                            end
           else if (mm_address == `REG_TH)            th                   <= mm_writedata[7:0];
           else if (mm_address == `MASK)  run_musk_and_real <= mm_writedata[0];
           else if (mm_address == `nMASK)  run_nmusk <= mm_writedata[0];
        end
    end
end



// Чтение avalone-mm mater
always @ (posedge clk)
begin
   if (~reset_n)
       mm_readdata <= {16'b0,1'b1,15'b0};
    else if (mm_chipselect & mm_read)
    begin
        if   (mm_address == `REG_STATUS) mm_readdata <= {16'b0,status};
    end
end

/////////////////////////////////
// Храниение предыдущего статуса процесса
reg pre_process_start;
always @ (posedge clk or negedge reset_n)
  if (~reset_n) pre_process_start <= 1'b1;
  else pre_process_start <= process_start;


wire process_start_tiggle;
assign process_start_tiggle = (~pre_process_start & process_start)?1'b1:1'b0;

//Область маскирования/демаскирования
wire masking_window_area ;
wire masking_window_area_musk ;
wire masking_window_area_nmusk ;
wire masking_window_border;


always @ (posedge clk or negedge reset_n)
begin
    if (~reset_n) begin
        x_cnt <= 12'd0;
        y_cnt <= 12'd0;
   end
    else if(sink_sop) begin
            x_cnt <= 12'd0;
           y_cnt <= 12'd0;
    end
    else if(sink_valid) begin
       if(x_cnt == VIDEO_W - 1'b1) begin
                 x_cnt <= 12'd0;
                  y_cnt <= y_cnt + 1'b1;
       end else begin
       x_cnt <= x_cnt + 1'b1;
       end
       myreg <= ((myreg ^ feedback) << 1) | !myreg[23];
    end
end

always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
        // reset
        state = st1;
    end
    else begin
        case(state)
            st1:begin
                if (x_cnt[3:0] != base ) begin
                    da[x_cnt[3:0]] = out;
                    state = st1;
                end
                else begin
                    state = st2;
                    da[x_cnt[3:0]] = out;
                end
            end
            st2:begin
                if (x_cnt[3:0] != base ) begin
                    d[x_cnt[3:0]] = out;

                    state = st2;
                end
                else begin
                    state = st1;
            end
            end
        endcase
    end
end



assign masking_window_area = (    x_cnt >= masking_active_x_start
                             && x_cnt <= (masking_active_x_start + masking_active_w)
                                      && y_cnt >= masking_active_y_start
                             && y_cnt <= (masking_active_y_start + masking_active_h)
                                      )?1'b1:1'b0;

assign masking_window_area_musk = (    x_cnt >= masking_active_x_start
                             && x_cnt <= (masking_active_x_start + masking_active_w/2)
                                      && y_cnt >= masking_active_y_start
                             && y_cnt <= (masking_active_y_start + masking_active_h)
                                      )?1'b1:1'b0;

assign masking_window_area_nmusk = (    x_cnt >= (masking_active_x_start  + masking_active_w/2)
                             && x_cnt <= (masking_active_x_start + masking_active_w)
                                      && y_cnt >= masking_active_y_start
                             && y_cnt <= (masking_active_y_start + masking_active_h)
                                      )?1'b1:1'b0;

assign masking_window_border = (( x_cnt == masking_active_x_start
                             || x_cnt == (masking_active_x_start + masking_active_w)
                                      || y_cnt == masking_active_y_start
                             || y_cnt == (masking_active_y_start + masking_active_h)
                                      ) && masking_window_area) ?1'b1:1'b0;

/////////////////////////////////////////////////
// AREA enable
reg       area_en;
reg [1:0] area_en_delay_cnt;
always @ (posedge clk or negedge reset_n)
begin
    if (~reset_n) begin
    area_en           <= 1'b0;
        area_en_delay_cnt <= 2'd0;
    end
    else if(process_start_tiggle) begin
    area_en           <= 1'b1;
        area_en_delay_cnt <= 2'd0;
    end
    else if(AREA_END & sink_eop )  begin
      if(area_en_delay_cnt == 2'd3) area_en <= 1'b0;// or delay x frame?
      else               area_en_delay_cnt <= area_en_delay_cnt + 1'b1;
    end
end

MASKING area_mask_demak(
.iR (sink_data_mask[23:16]),
.iG (sink_data_mask[15: 8]),
.iB (sink_data_mask[ 7: 0]),
.VS (sink_sop & sink_valid),

.SMSK(smsk),
.SMSK_F(smsk_f),
.TH(th),
.ACTIV_C (masking_window_area & sink_valid) ,// masking-window area
.ACTIV_V (sink_valid) , // full-screen

.VIDEO_CLK  ( clk   ),
.MASK_DEMASK   ( res  ),  // masking data
.SW_FUC_ALL_CEN( masking_mode) ,//
.AREA_END ( AREA_END) ,
.Y   ( Y ),
.S   (S ),
.END_STEP  (END_STEP ),
.AREA_DATA (AREA_DATA ),
.SUM(sum)

);//
wire  [15:0] AREA_DATA ;
wire  [9:0]  END_STEP ;
wire         AREA_END  ;
wire  [7:0]     S  ;
wire  [17:0]    Y  ;
//-----
wire [15:0] status;
wire [31:0]  sum;
assign status  = { ~area_en,5'b0,END_STEP} ;



I2C_AREA_Config vcm_i2c(
                .iCLK(clk50),//clk_50
                .ENABLE(vcm_en),    // enable
                .iRST_N(~sink_eop), // trigger
                .AREA_DATA(AREA_DATA),
                .END(),//vcm_i2c_end

                .I2C_SCLK(vcm_i2c_scl),
                .I2C_SDAT(vcm_i2c_sda)
                );



endmodule