Task Lola

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    20:09:51 11/04/2018
// Design Name:
// Module Name:    runlight
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RunLolaOne #(parameter DIGINIT = 0, DIGITA = DIGINIT + 3)                    // 21
(
    input  clk,
    output [3:0]row
);

// 25 wires.
wire [DIGITA:0]add;
wire [2:0]add_stp;

// Register counter.
reg  [DIGITA:0]RG = {(DIGINIT + 4){1'b0}};
// Register shifter
reg [3:0]rowGO = 4'b0000;
reg [2:0]step_r = 3'b000;

assign row[3:0] = rowGO[3:0];

assign add[DIGITA:0] = RG[DIGITA:0] + 1'b1;

assign add_stp[2:0] = step_r[2:0] + 1'b1;

// Register shifter run
always@(posedge clk) begin

            if(RG[DIGITA:0] == {{(DIGINIT + 3){1'b0}},{1'b1}}) begin

                if(step_r[2:0] == 3'b000) begin
                    rowGO[3:0] <= 4'b1110;

                end

                if(step_r[2:0] == 3'b100) begin
                    rowGO[3:0] <= 4'b0111;

                end

            end

            if(RG[DIGITA:0] == {{(DIGINIT + 2){1'b0}},{2'b10}}) begin

                        if(step_r[2:0] >= 3'b000 && step_r[2:0] <= 3'b011)
                       begin
                            rowGO <= {rowGO[0], rowGO[3:1]};
                        end

                       if(step_r[2:0] >= 3'b100 && step_r[2:0] <= 3'b111)
                        begin
                            rowGO <= {rowGO[2:0], rowGO[3]};
                        end

                    step_r[2:0] <= add_stp[2:0];

            end

            RG[DIGITA:0] <= add[DIGITA:0];
end

endmodule