diff --git a/litex/boards/platforms/beaglewire.py b/litex/boards/platforms/beaglewire.py
new file mode 100644
index 00000000..074b7aee
--- /dev/null
+++ b/litex/boards/platforms/beaglewire.py
@@ -0,0 +1,64 @@
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import IceStormProgrammer
+
+
+_io = [
+    ("user_led", 0, Pins("28"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("29"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("31"), IOStandard("LVCMOS33")),
+    ("user_led", 3, Pins("32"), IOStandard("LVCMOS33")),
+
+    ("user_sw", 0, Pins("33"), IOStandard("LVCMOS33")),
+    ("user_sw", 1, Pins("34"), IOStandard("LVCMOS33")),
+
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")),
+        Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("68"), IOStandard("LVCMOS33"))
+    ),
+
+    ("sdram_clock", 0, Pins("93"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+    ("sdram", 0,
+        Subsignal("a", Pins("118 117 116 101 81 83 90 91 82 84 119 85 87")),
+        Subsignal("dq", Pins("96 97 98 99 95 80 79 78")),
+        Subsignal("we_n", Pins("128")),
+        Subsignal("ras_n", Pins("124")),
+        Subsignal("cas_n", Pins("125")),
+        Subsignal("cs_n", Pins("137")),
+        Subsignal("cke", Pins("88")),
+        Subsignal("ba", Pins("121 120")),
+        Subsignal("dm", Pins("94")),
+        IOStandard("LVCMOS33"), Misc("SLEW=FAST")
+    ),
+
+    ("serial", 0,
+        Subsignal("tx", Pins("105"), IOStandard("LVCMOS33")),  # Grove4 D0
+        Subsignal("rx", Pins("106"), IOStandard("LVCMOS33"))   # GROVE4 D1
+    ),
+
+    ("clk100", 0, Pins("61"), IOStandard("LVCMOS33"))
+]
+
+_connectors = [
+    ("PMOD1", "38 41 43 45 37 39 42 44"),
+    ("PMOD2", "48 52 56 62 47 49 55 60"),
+    ("PMOD3", "107 112 114 129 110 113 115 130"),
+    ("PMOD4", "4 8 10 11 7 9 15 12"),
+    ("GROVE1", "73 74"),
+    ("GROVE2", "75 76"),
+    ("GROVE3", "102 104")
+]
+
+
+class Platform(LatticePlatform):
+    default_clk_name = "clk100"
+    default_clk_period = 10
+
+    def __init__(self):
+        LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", _io, _connectors,
+                                 toolchain="icestorm")
+
+    def create_programmer(self):
+        return IceStormProgrammer()
diff --git a/litex/boards/targets/beaglewire.py b/litex/boards/targets/beaglewire.py
new file mode 100755
index 00000000..1bba7e5a
--- /dev/null
+++ b/litex/boards/targets/beaglewire.py
@@ -0,0 +1,70 @@
+#!/usr/bin/env python3
+
+import argparse
+from fractions import Fraction
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.boards.platforms import beaglewire
+
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import SDRAMModule
+from litedram.phy import GENSDRPHY
+
+class IS42S83200(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings (-7 speedgrade)
+    tRP   = 20
+    tRCD  = 20
+    tWR   = 20
+    tWTR  = 2
+    tREFI = 64*1000*1000/8192
+    tRFC  = 70
+
+class _CRG(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys_ps = ClockDomain()
+        self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+        clk100 = platform.request("clk100")
+
+        self.comb += platform.request("sdram_clock").eq(clk100)
+        self.comb += self.cd_sys.clk.eq(clk100)
+        self.comb += self.cd_sys_ps.clk.eq(clk100)
+
+class BaseSoC(SoCSDRAM):
+    def __init__(self, **kwargs):
+        clk_freq = 100*1000000
+        platform = beaglewire.Platform()
+        SoCSDRAM.__init__(self, platform, clk_freq,
+                          **kwargs)
+
+        self.submodules.crg = _CRG(platform)
+
+        if not self.integrated_main_ram_size:
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            sdram_module = IS42S83200(clk_freq, "1:1")
+            self.register_sdram(self.sdrphy,
+                                sdram_module.geom_settings,
+                                sdram_module.timing_settings)
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC port to Beaglewire")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+if __name__ == "__main__":
+    main()