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Connect4_main_module

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  1.  
  2. module project(
  3. CLOCK_50, // On Board 50 MHz
  4. // Your inputs and outputs here
  5. KEY,
  6. SW,
  7. // The ports below are for the VGA output. Do not change.
  8. VGA_CLK, // VGA Clock
  9. VGA_HS, // VGA H_SYNC
  10. VGA_VS, // VGA V_SYNC
  11. VGA_BLANK_N, // VGA BLANK
  12. VGA_SYNC_N, // VGA SYNC
  13. VGA_R, // VGA Red[9:0]
  14. VGA_G, // VGA Green[9:0]
  15. VGA_B
  16. );
  17.  
  18.  
  19. // Declare your inputs and outputs here
  20. // Do not change the following outputs
  21. output VGA_CLK; // VGA Clock
  22. output VGA_HS; // VGA H_SYNC
  23. output VGA_VS; // VGA V_SYNC
  24. output VGA_BLANK_N; // VGA BLANK
  25. output VGA_SYNC_N; // VGA SYNC
  26. output [9:0] VGA_R; // VGA Red[9:0]
  27. output [9:0] VGA_G; // VGA Green[9:0]
  28. output [9:0] VGA_B; // VGA Blue[9:0]
  29.  
  30.  
  31. // Create an Instance of a VGA controller - there can be only one!
  32. // Define the number of colours as well as the initial background
  33. // image file (.MIF) for the controller.
  34. vga_adapter VGA(
  35. .resetn(resetn),
  36. .clock(CLOCK_50),
  37. .colour(colour),
  38. .x(x),
  39. .y(y),
  40. .plot(writeEn),
  41. /* Signals for the DAC to drive the monitor. */
  42. .VGA_R(VGA_R),
  43. .VGA_G(VGA_G),
  44. .VGA_B(VGA_B),
  45. .VGA_HS(VGA_HS),
  46. .VGA_VS(VGA_VS),
  47. .VGA_BLANK(VGA_BLANK_N),
  48. .VGA_SYNC(VGA_SYNC_N),
  49. .VGA_CLK(VGA_CLK));
  50. defparam VGA.RESOLUTION = "160x120";
  51. defparam VGA.MONOCHROME = "FALSE";
  52. defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
  53. defparam VGA.BACKGROUND_IMAGE = "black.mif";
  54.  
  55. // Put your code here. Your code should produce signals x,y,colour and writeEn/plot
  56. // for the VGA controller, in addition to any other functionality your design may require.
  57.  
  58.  
  59. //............................................
  60. // set KEYs
  61. input [3:0] KEY;
  62. wire resetn = ~KEY[0];
  63. wire left_shift_column = ~KEY[1];
  64. wire right_shift_column = ~KEY[2];
  65. wire drop_chip = ~KEY[3];
  66.  
  67. wire [2:0] current_column = 3'd3;
  68.  
  69. //...........................................
  70. // RAM variables
  71. wire [5:0] ad; // ram address
  72. wire [1:0] value; // ram out
  73. wire [1:0] data; // ram data
  74. wire write_ram ; // ram write_ram
  75.  
  76. //...........................................
  77. //VGA
  78. wire [7:0] x;
  79. wire [6:0] y;
  80. wire [2:0] colour;
  81. wire write_vga;
  82. //............................................
  83.  
  84. // start with player 1's turn
  85. wire current_player = 2'b01;
  86.  
  87. // for contorller, data_path, and draw_chip
  88. wire drop_chip;
  89. wire is_top_empty;
  90. wire found_empty;
  91. wire choosing_column;
  92. wire ld_check_top;
  93. wire ld_find_spot;
  94. wire read_address;
  95.  
  96. wire [3:0] counter_x;
  97. wire [3:0] counter_y;
  98. wire draw_chip;
  99. wire finished_drawing;
  100.  
  101. //...............................................
  102.  
  103.  
  104.  
  105. // has the memory for each board location
  106. ram64x2 memory(.clock(CLOCK_50),
  107. .address(ad),
  108. .data(data),
  109. .wren(write_ram ),
  110. .q(value)
  111. );
  112.  
  113. // Draws the board
  114. draw_board_connect4 board(.clk(CLOCK_50),
  115. .resetn(resetn),
  116. .write(write_vga),
  117. .x(x),
  118. .y(y),
  119. .colour(colour)
  120. );
  121.  
  122. // control
  123. control C0(.clk(CLOCK_50),
  124. .resetn(resetn)
  125. .drop_chip(drop_chip),
  126. .is_top_empty(is_top_empty),
  127. .found_empty(found_empty),
  128. .finished_drawing(finised_drawing),
  129. .choosing_column(choosing_column),
  130. .ld_check_top(ld_check_top),
  131. .ld_find_spot(ld_find_spot),
  132. .draw_chip(draw_chip),
  133. .writeEn_ram(write_ram),
  134. .writeEn_vga(write_vga),
  135. .read_address(read_address)
  136. );
  137.  
  138. // data_path
  139. datapath d0(.clk(CLOCK_50),
  140. .resetn(resetn),
  141. .choosing_column(choosing_column),
  142. .left_shift_column(left_shift_column),
  143. .right_shift_column(right_shift_column),
  144. .current_column(current_column),
  145. .current_player(current_player),
  146. .value(value),
  147. .address(ad),
  148. .data(data),
  149. .colour(colour),
  150. .x(x),
  151. .y(y),
  152. .ld_check_top(ld_check_top),
  153. .read_address(read_address),
  154. .ld_find_spot(ld_find_spot),
  155. .draw_chip(draw_chip),
  156. .finished_drawing(finished_drawing),
  157. .check_top(check_top),
  158. .is_top_empty(is_top_empty),
  159. .found_empty(found_empty)
  160. );
  161.  
  162. //draws a single chip
  163. draw_chip dc(.clk(CLOCK_50),
  164. .resetn(resetn),
  165. .counter_x(counter_x),
  166. .counter_y(counter_y),
  167. .draw_chip(draw_chip),
  168. .finished_drawing(finished_drawing)
  169. );
  170.  
  171. endmodule
  172.  
  173.  
  174.  
  175.  
  176. //......................................CONTROLLER...........................................................
  177.  
  178. module control(clk, resetn, drop_chip, is_top_empty, found_empty, finished_drawing, choosing_column,
  179. ld_check_top, ld_find_spot, draw_chip, writeEn_ram, writeEn_vga, read_address
  180. );
  181.  
  182. input clk, resetn;
  183.  
  184. // state controllers
  185. input drop_chip; // ~KEY[3]
  186. input is_top_empty;
  187. input found_empty;
  188. input finished_drawing;
  189.  
  190. //for data_path inputs
  191. output reg choosing_column;
  192. output reg ld_check_top;
  193. output reg ld_find_spot;
  194. output reg draw_chip;
  195. output reg writeEn_ram;
  196. output reg writeEn_vga;
  197. output reg read_address;
  198.  
  199. reg [3:0] current_state, next_state;
  200.  
  201. localparam //REDRAW_BOARD
  202. CHOOSE_COLUMN = 4'd0,
  203. CHECK_TOP = 4'd1
  204. SET_ADDRESS = 4'd2,
  205. READ_ADDRESS = 4'd3;
  206. SET_X_Y = 4'd4,
  207. DRAW_SQUARE = 4'd5;
  208.  
  209. always@(*)
  210. begin: state_table
  211. case (current_state)
  212.  
  213. CHOOSE_COLUMN: next_state = drop_chip ? CHECK_TOP: CHOOSE_COLUMN;
  214.  
  215. CHECK_TOP_SET_ADDRESS: next_state = CHECK_TOP_READ_ADDRESS;
  216. CHECK_TOP_READ_ADDRESS: next_state = is_top_empty ? SET_ADDRESS: CHOOSE_COLUMN;
  217.  
  218. READ_ADDRESS: next_state = found_empty ? DRAW_SQUARE: READ_ADDRESS;
  219.  
  220. DRAW_SQUARE: next_state = finished_drawing ? CHOOSE_COLUMN : DRAW_SQUARE;
  221.  
  222. default: next_state = CHOOSE_COLUMN;
  223. endcase
  224. end
  225.  
  226.  
  227. // Output logic aka all of our datapath control signals
  228. always @(*)
  229. begin: enable_signals
  230.  
  231. // by default set all to
  232. writeEn_ram = 1'b0;
  233. writeEn_vga = 1'b0;
  234. read_address = 1'b0;
  235. choosing_column = 1'b0;
  236. ld_check_top = 1'b0;
  237. ld_find_spot = 1'b0;
  238. draw_chip = 1'b0;
  239.  
  240.  
  241. case (current_state)
  242.  
  243. CHOOSE_COLUMN: begin
  244. choosing_column = 1'b1;
  245. ld_check_top = 1'b0;
  246. end
  247.  
  248. CHECK_TOP_SET_ADDRESS: begin
  249. read_address = 1'b0;
  250. ld_check_top = 1'b1;
  251. end
  252.  
  253. CHECK_TOP_READ_ADDRESS: begin
  254. read_address = 1'b1;
  255. ld_check_top = 1'b0;
  256. end
  257.  
  258. READ_ADDRESS: begin
  259. ld_check_top = 1'b0;
  260. ld_find_spot = 1'b1;
  261. end
  262.  
  263. DRAW_SQUARE: begin
  264. ld_check_top = 1'b0;
  265. draw_chip = 1'b1;
  266. writeEn_ram = 1'b1;
  267. writeEn_vga = 1'b1;
  268. end
  269.  
  270. endcase
  271. end
  272.  
  273. endmodule
  274.  
  275.  
  276. //......................................DATA_PATH...........................................................
  277.  
  278. module data_path(clk, resetn, choosing_column, left_shift_column, right_shift_column, current_column,
  279. current_player, value, address, data, colour, x, y, ld_check_top, read_address,
  280. ld_find_spot, draw_chip, finished_drawing, check_top, is_top_empty, found_empty);
  281.  
  282. input clk, resetn;
  283.  
  284. input choosing_column;
  285. input left_shift_column;
  286. input right_shift_column;
  287.  
  288. output reg [3:0] current_column;
  289. output reg [1:0] current_player;
  290.  
  291. //ram
  292. input [1:0] value;
  293. output reg [5:0] address;
  294. output reg [1:0] data;
  295.  
  296. //vga
  297. output reg [2:0] colour;
  298. output reg [7:0] x;
  299. output reg [7:0] y;
  300.  
  301. // data_path inputs
  302. input ld_check_top;
  303. input read_address;
  304. input ld_find_spot;
  305. input draw_chip;
  306. input finished_drawing;
  307.  
  308. // controller inputs
  309. output reg check_top;
  310. output reg is_top_empty;
  311. output reg found_empty;
  312.  
  313.  
  314. reg [7:0] map_x = 7'd52; // middle column
  315. reg [7:0] map_y = 7'd84; // bottom row
  316.  
  317. localparam PLAYER1_COLOUR = 3'b100, // RED
  318. PLAYER2_COLOUR = 3'b001; // BLUE
  319.  
  320.  
  321.  
  322. always @ (posedge clk)
  323. begin
  324.  
  325. // state 0: CHOOSE_COLUMN
  326. if (choosing_column) begin
  327. if (left_shift_column) begin
  328. if ( current_column > 3'd0) begin
  329. current_column <= current_column - 1'b1;
  330. map_x <= map_x - 7'd16;
  331. end
  332. end
  333.  
  334. if (right_shift_column) begin
  335. if (current_column < 3'd6) begin
  336. current_column <= current_column + 1'b1;
  337. map_x <= map_x + 7'd16;
  338. end
  339. end
  340. end
  341.  
  342. // state 1: CHECK_TOP_SET_ADDRESS
  343. if (ld_check_top) begin
  344. address <= current_column + 6'd35;
  345. // read write_ram = 1'b0;
  346. //check out == 2'b00
  347. end
  348.  
  349. // state 2: CHECK_TOP_READ_ADDRESS
  350. if(read_address) begin
  351.  
  352. if (value == 2'b00) begin
  353. is_top_empty <= 1'b1;
  354. address <= current_column
  355. end
  356. else begin
  357. is_top_empty <= 1'b0;
  358. end
  359.  
  360. // state 3: READ_ADDRESS
  361. if (ld_find_spot) begin
  362.  
  363. if(value == 2'b01 || value == 2'b10) begin
  364. address <= address + 7'd7;
  365. map_y <= map_y - 7'd16;
  366. found_empty <= 1'b0;
  367. end
  368.  
  369. else begin
  370. found_empty <= 1'b1;
  371. data <= current_player;
  372. end
  373.  
  374. end
  375.  
  376. // state 4: DRAW_CHIP
  377. if (draw_chip) begin
  378. write_vga = 1'b1;
  379. x <= map_x + counter_x;
  380. y <= map_y + counter_y;
  381.  
  382. // set colour to match player
  383. if (current_player == 2'b01) begin
  384. colour <= PLAYER1_COLOUR;
  385. end
  386.  
  387. else begin
  388. colour <= PLAYER2_COLOUR;
  389. end
  390. end
  391.  
  392. if (finished_drawing) begin
  393. if (current_player == 2'b01) begin
  394. current_player <= 2'b10;
  395. end
  396.  
  397. else if (current_player == 2'b10) begin
  398. current_player <= 2'b01;
  399. end
  400.  
  401. end
  402. end
  403.  
  404. endmodule
  405.  
  406. //...........................................................................................................
  407.  
  408. module draw_chip (clk, resetn, counter_x, counter_y, draw_chip, finished_drawing);
  409.  
  410. input draw_chip;
  411. input clk;
  412. input resetn;
  413.  
  414. output reg [3:0] counter_x;
  415. output reg [3:0] counter_y;
  416.  
  417. output finished_drawing;
  418.  
  419. localparam SQUARE_MAX_SIZE = 4'd11; // 11 pixeles starting at 0
  420.  
  421. always @ (posedge clk) begin
  422.  
  423. if (draw_chip) begin
  424.  
  425. if(counter_x < SQUARE_MAX_SIZE) begin
  426. counter_x <= counter_x + 4'd1; // add 1 to counter x
  427. end
  428.  
  429. else if (counter_x == SQUARE_MAX_SIZE) begin // overlap when counter x reaches the end
  430. counter_x <= 4'd0; // reset counter x to 0
  431. counter_y <= counter_y + 4'd1; // increment counter y
  432. end
  433. end
  434.  
  435.  
  436. if (~resetn) begin
  437. counter_x <= 4'd0;
  438. counter_y <= 4'd0;
  439. end
  440.  
  441. if (finished_drawing) begin
  442. counter_x <= 4'd0;
  443. counter_y <= 4'd0;
  444. end
  445. end
  446.  
  447. assign finished_drawing = (counter_y > VERTICAL_MAX);
  448.  
  449. endmodule
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