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- module project(
- CLOCK_50, // On Board 50 MHz
- // Your inputs and outputs here
- KEY,
- SW,
- // The ports below are for the VGA output. Do not change.
- VGA_CLK, // VGA Clock
- VGA_HS, // VGA H_SYNC
- VGA_VS, // VGA V_SYNC
- VGA_BLANK_N, // VGA BLANK
- VGA_SYNC_N, // VGA SYNC
- VGA_R, // VGA Red[9:0]
- VGA_G, // VGA Green[9:0]
- VGA_B
- );
- // Declare your inputs and outputs here
- // Do not change the following outputs
- output VGA_CLK; // VGA Clock
- output VGA_HS; // VGA H_SYNC
- output VGA_VS; // VGA V_SYNC
- output VGA_BLANK_N; // VGA BLANK
- output VGA_SYNC_N; // VGA SYNC
- output [9:0] VGA_R; // VGA Red[9:0]
- output [9:0] VGA_G; // VGA Green[9:0]
- output [9:0] VGA_B; // VGA Blue[9:0]
- // Create an Instance of a VGA controller - there can be only one!
- // Define the number of colours as well as the initial background
- // image file (.MIF) for the controller.
- vga_adapter VGA(
- .resetn(resetn),
- .clock(CLOCK_50),
- .colour(colour),
- .x(x),
- .y(y),
- .plot(writeEn),
- /* Signals for the DAC to drive the monitor. */
- .VGA_R(VGA_R),
- .VGA_G(VGA_G),
- .VGA_B(VGA_B),
- .VGA_HS(VGA_HS),
- .VGA_VS(VGA_VS),
- .VGA_BLANK(VGA_BLANK_N),
- .VGA_SYNC(VGA_SYNC_N),
- .VGA_CLK(VGA_CLK));
- defparam VGA.RESOLUTION = "160x120";
- defparam VGA.MONOCHROME = "FALSE";
- defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
- defparam VGA.BACKGROUND_IMAGE = "black.mif";
- // Put your code here. Your code should produce signals x,y,colour and writeEn/plot
- // for the VGA controller, in addition to any other functionality your design may require.
- //............................................
- // set KEYs
- input [3:0] KEY;
- wire resetn = ~KEY[0];
- wire left_shift_column = ~KEY[1];
- wire right_shift_column = ~KEY[2];
- wire drop_chip = ~KEY[3];
- wire [2:0] current_column = 3'd3;
- //...........................................
- // RAM variables
- wire [5:0] ad; // ram address
- wire [1:0] value; // ram out
- wire [1:0] data; // ram data
- wire write_ram ; // ram write_ram
- //...........................................
- //VGA
- wire [7:0] x;
- wire [6:0] y;
- wire [2:0] colour;
- wire write_vga;
- //............................................
- // start with player 1's turn
- wire current_player = 2'b01;
- // for contorller, data_path, and draw_chip
- wire drop_chip;
- wire is_top_empty;
- wire found_empty;
- wire choosing_column;
- wire ld_check_top;
- wire ld_find_spot;
- wire read_address;
- wire [3:0] counter_x;
- wire [3:0] counter_y;
- wire draw_chip;
- wire finished_drawing;
- //...............................................
- // has the memory for each board location
- ram64x2 memory(.clock(CLOCK_50),
- .address(ad),
- .data(data),
- .wren(write_ram ),
- .q(value)
- );
- // Draws the board
- draw_board_connect4 board(.clk(CLOCK_50),
- .resetn(resetn),
- .write(write_vga),
- .x(x),
- .y(y),
- .colour(colour)
- );
- // control
- control C0(.clk(CLOCK_50),
- .resetn(resetn)
- .drop_chip(drop_chip),
- .is_top_empty(is_top_empty),
- .found_empty(found_empty),
- .finished_drawing(finised_drawing),
- .choosing_column(choosing_column),
- .ld_check_top(ld_check_top),
- .ld_find_spot(ld_find_spot),
- .draw_chip(draw_chip),
- .writeEn_ram(write_ram),
- .writeEn_vga(write_vga),
- .read_address(read_address)
- );
- // data_path
- datapath d0(.clk(CLOCK_50),
- .resetn(resetn),
- .choosing_column(choosing_column),
- .left_shift_column(left_shift_column),
- .right_shift_column(right_shift_column),
- .current_column(current_column),
- .current_player(current_player),
- .value(value),
- .address(ad),
- .data(data),
- .colour(colour),
- .x(x),
- .y(y),
- .ld_check_top(ld_check_top),
- .read_address(read_address),
- .ld_find_spot(ld_find_spot),
- .draw_chip(draw_chip),
- .finished_drawing(finished_drawing),
- .check_top(check_top),
- .is_top_empty(is_top_empty),
- .found_empty(found_empty)
- );
- //draws a single chip
- draw_chip dc(.clk(CLOCK_50),
- .resetn(resetn),
- .counter_x(counter_x),
- .counter_y(counter_y),
- .draw_chip(draw_chip),
- .finished_drawing(finished_drawing)
- );
- endmodule
- //......................................CONTROLLER...........................................................
- module control(clk, resetn, drop_chip, is_top_empty, found_empty, finished_drawing, choosing_column,
- ld_check_top, ld_find_spot, draw_chip, writeEn_ram, writeEn_vga, read_address
- );
- input clk, resetn;
- // state controllers
- input drop_chip; // ~KEY[3]
- input is_top_empty;
- input found_empty;
- input finished_drawing;
- //for data_path inputs
- output reg choosing_column;
- output reg ld_check_top;
- output reg ld_find_spot;
- output reg draw_chip;
- output reg writeEn_ram;
- output reg writeEn_vga;
- output reg read_address;
- reg [3:0] current_state, next_state;
- localparam //REDRAW_BOARD
- CHOOSE_COLUMN = 4'd0,
- CHECK_TOP = 4'd1
- SET_ADDRESS = 4'd2,
- READ_ADDRESS = 4'd3;
- SET_X_Y = 4'd4,
- DRAW_SQUARE = 4'd5;
- always@(*)
- begin: state_table
- case (current_state)
- CHOOSE_COLUMN: next_state = drop_chip ? CHECK_TOP: CHOOSE_COLUMN;
- CHECK_TOP_SET_ADDRESS: next_state = CHECK_TOP_READ_ADDRESS;
- CHECK_TOP_READ_ADDRESS: next_state = is_top_empty ? SET_ADDRESS: CHOOSE_COLUMN;
- READ_ADDRESS: next_state = found_empty ? DRAW_SQUARE: READ_ADDRESS;
- DRAW_SQUARE: next_state = finished_drawing ? CHOOSE_COLUMN : DRAW_SQUARE;
- default: next_state = CHOOSE_COLUMN;
- endcase
- end
- // Output logic aka all of our datapath control signals
- always @(*)
- begin: enable_signals
- // by default set all to
- writeEn_ram = 1'b0;
- writeEn_vga = 1'b0;
- read_address = 1'b0;
- choosing_column = 1'b0;
- ld_check_top = 1'b0;
- ld_find_spot = 1'b0;
- draw_chip = 1'b0;
- case (current_state)
- CHOOSE_COLUMN: begin
- choosing_column = 1'b1;
- ld_check_top = 1'b0;
- end
- CHECK_TOP_SET_ADDRESS: begin
- read_address = 1'b0;
- ld_check_top = 1'b1;
- end
- CHECK_TOP_READ_ADDRESS: begin
- read_address = 1'b1;
- ld_check_top = 1'b0;
- end
- READ_ADDRESS: begin
- ld_check_top = 1'b0;
- ld_find_spot = 1'b1;
- end
- DRAW_SQUARE: begin
- ld_check_top = 1'b0;
- draw_chip = 1'b1;
- writeEn_ram = 1'b1;
- writeEn_vga = 1'b1;
- end
- endcase
- end
- endmodule
- //......................................DATA_PATH...........................................................
- module data_path(clk, resetn, choosing_column, left_shift_column, right_shift_column, current_column,
- current_player, value, address, data, colour, x, y, ld_check_top, read_address,
- ld_find_spot, draw_chip, finished_drawing, check_top, is_top_empty, found_empty);
- input clk, resetn;
- input choosing_column;
- input left_shift_column;
- input right_shift_column;
- output reg [3:0] current_column;
- output reg [1:0] current_player;
- //ram
- input [1:0] value;
- output reg [5:0] address;
- output reg [1:0] data;
- //vga
- output reg [2:0] colour;
- output reg [7:0] x;
- output reg [7:0] y;
- // data_path inputs
- input ld_check_top;
- input read_address;
- input ld_find_spot;
- input draw_chip;
- input finished_drawing;
- // controller inputs
- output reg check_top;
- output reg is_top_empty;
- output reg found_empty;
- reg [7:0] map_x = 7'd52; // middle column
- reg [7:0] map_y = 7'd84; // bottom row
- localparam PLAYER1_COLOUR = 3'b100, // RED
- PLAYER2_COLOUR = 3'b001; // BLUE
- always @ (posedge clk)
- begin
- // state 0: CHOOSE_COLUMN
- if (choosing_column) begin
- if (left_shift_column) begin
- if ( current_column > 3'd0) begin
- current_column <= current_column - 1'b1;
- map_x <= map_x - 7'd16;
- end
- end
- if (right_shift_column) begin
- if (current_column < 3'd6) begin
- current_column <= current_column + 1'b1;
- map_x <= map_x + 7'd16;
- end
- end
- end
- // state 1: CHECK_TOP_SET_ADDRESS
- if (ld_check_top) begin
- address <= current_column + 6'd35;
- // read write_ram = 1'b0;
- //check out == 2'b00
- end
- // state 2: CHECK_TOP_READ_ADDRESS
- if(read_address) begin
- if (value == 2'b00) begin
- is_top_empty <= 1'b1;
- address <= current_column
- end
- else begin
- is_top_empty <= 1'b0;
- end
- // state 3: READ_ADDRESS
- if (ld_find_spot) begin
- if(value == 2'b01 || value == 2'b10) begin
- address <= address + 7'd7;
- map_y <= map_y - 7'd16;
- found_empty <= 1'b0;
- end
- else begin
- found_empty <= 1'b1;
- data <= current_player;
- end
- end
- // state 4: DRAW_CHIP
- if (draw_chip) begin
- write_vga = 1'b1;
- x <= map_x + counter_x;
- y <= map_y + counter_y;
- // set colour to match player
- if (current_player == 2'b01) begin
- colour <= PLAYER1_COLOUR;
- end
- else begin
- colour <= PLAYER2_COLOUR;
- end
- end
- if (finished_drawing) begin
- if (current_player == 2'b01) begin
- current_player <= 2'b10;
- end
- else if (current_player == 2'b10) begin
- current_player <= 2'b01;
- end
- end
- end
- endmodule
- //...........................................................................................................
- module draw_chip (clk, resetn, counter_x, counter_y, draw_chip, finished_drawing);
- input draw_chip;
- input clk;
- input resetn;
- output reg [3:0] counter_x;
- output reg [3:0] counter_y;
- output finished_drawing;
- localparam SQUARE_MAX_SIZE = 4'd11; // 11 pixeles starting at 0
- always @ (posedge clk) begin
- if (draw_chip) begin
- if(counter_x < SQUARE_MAX_SIZE) begin
- counter_x <= counter_x + 4'd1; // add 1 to counter x
- end
- else if (counter_x == SQUARE_MAX_SIZE) begin // overlap when counter x reaches the end
- counter_x <= 4'd0; // reset counter x to 0
- counter_y <= counter_y + 4'd1; // increment counter y
- end
- end
- if (~resetn) begin
- counter_x <= 4'd0;
- counter_y <= 4'd0;
- end
- if (finished_drawing) begin
- counter_x <= 4'd0;
- counter_y <= 4'd0;
- end
- end
- assign finished_drawing = (counter_y > VERTICAL_MAX);
- endmodule
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