diff --git a/cores/usb/rtl/usb_ep_buf.v b/cores/usb/rtl/usb_ep_buf.v
index 3743d13..229b47d 100644
--- a/cores/usb/rtl/usb_ep_buf.v
+++ b/cores/usb/rtl/usb_ep_buf.v
@@ -46,6 +46,7 @@ module usb_ep_buf #(
    input  wire wr_en_0,
    input  wire wr_clk
 );
+`ifdef XXX
    // MODE 0:  256 x 16
    // MODE 1:  512 x 8
    // MODE 2: 1024 x 4
@@ -283,5 +284,55 @@ module usb_ep_buf #(
                assign ram_wdata = wr_data_0_ram[i*16+:16];
        end
    endgenerate
+`else
+
+   reg [31:0] ram[0:512];
+   reg [31:0] ram_rd;
+   reg [1:0] rds;
+   reg [7:0] rdm;
+
+   always @(posedge rd_clk)
+   begin
+       if (rd_en_0) begin
+           if (RWIDTH == 32)
+               ram_rd <= ram[rd_addr_0];
+           else if (RWIDTH == 8)
+               ram_rd <= ram[rd_addr_0[ARW-1:2]];
+
+           rds <= rd_addr_0[1:0];
+       end
+   end
+
+   always @(*)
+       case (rds)
+           2'b00: rdm <= ram_rd[ 7: 0];
+           2'b01: rdm <= ram_rd[15: 8];
+           2'b10: rdm <= ram_rd[23:16];
+           2'b11: rdm <= ram_rd[31:24];
+       endcase
+
+   assign rd_data_1 = (RWIDTH == 32) ? ram_rd : rdm;
+
+   always @(posedge wr_clk)
+   begin
+       if (wr_en_0) begin
+           if (WWIDTH == 32) begin
+               ram[wr_addr_0] <= wr_data_0;
+           end else if (WWIDTH == 8) begin
+               if (wr_addr_0[1:0] == 2'b00)
+                   ram[wr_addr_0[AWW-1:2]][ 7: 0] <= wr_data_0;
+
+               if (wr_addr_0[1:0] == 2'b01)
+                   ram[wr_addr_0[AWW-1:2]][15: 8] <= wr_data_0;
+
+               if (wr_addr_0[1:0] == 2'b10)
+                   ram[wr_addr_0[AWW-1:2]][23:16] <= wr_data_0;
+
+               if (wr_addr_0[1:0] == 2'b11)
+                   ram[wr_addr_0[AWW-1:2]][31:24] <= wr_data_0;
+           end
+       end
+   end

+`endif
 endmodule // usb_ep_buf
diff --git a/cores/usb/rtl/usb_ep_status.v b/cores/usb/rtl/usb_ep_status.v
index 5bad34a..28fb59b 100644
--- a/cores/usb/rtl/usb_ep_status.v
+++ b/cores/usb/rtl/usb_ep_status.v
@@ -98,6 +98,7 @@ module usb_ep_status (
            s_dout_3 <= s_zero_2 ? 16'h0000 : dout_2;

    // RAM element
+`ifdef XXX
    SB_RAM40_4K #(
 `ifdef SIM
        .INIT_FILE("usb_ep_status.hex"),
@@ -117,5 +118,23 @@ module usb_ep_status (
        .WCLKE(we_1),
        .WE(1'b1)
    );
+`else
+   reg [15:0] ram[0:255];
+   reg [15:0] ram_rd;
+
+`ifdef SIM
+   initial
+       $readmemh("usb_ep_status.hex", ram);
+`endif
+
+   always @(posedge clk)
+   begin
+       ram_rd <= ram[addr_1];
+       if (we_1)
+           ram[addr_1] <= din_1;
+   end
+
+   assign dout_2 = ram_rd;
+`endif

 endmodule // usb_ep_status
diff --git a/cores/usb/rtl/usb_trans.v b/cores/usb/rtl/usb_trans.v
index c4cae6c..8410bf8 100644
--- a/cores/usb/rtl/usb_trans.v
+++ b/cores/usb/rtl/usb_trans.v
@@ -195,6 +195,7 @@ module usb_trans #(
            mc_pc_nxt <= mc_pc + 1;

    // Microcode ROM
+`ifdef XXX
    SB_RAM40_4K #(
        .INIT_FILE("usb_trans_mc.hex"),
        .WRITE_MODE(0),
@@ -212,6 +213,18 @@ module usb_trans #(
        .WCLKE(1'b0),
        .WE(1'b0)
    );
+`else
+   reg [15:0] rom[0:255];
+   reg [15:0] rom_rd;
+
+   initial
+       $readmemh("usb_trans_mc.hex", rom);
+
+   always @(posedge clk)
+       rom_rd <= rom[mc_pc];
+
+   assign mc_opcode = rom_rd;
+`endif

    // Decode opcodes
    assign mc_op_ld      = mc_opcode[15:12] == 4'b0001;