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- module cnt(CLK,CE,Q,CEO);
- input CLK,CE;
- output reg [27:0] Q;
- output CEO;
- always @(posedge CLK)
- if(CE)
- if(Q != 28'd250000)
- Q <= Q + 1;
- else
- Q <= 28'd0;
- assign CEO = CE & (Q == 28'd250000);
- endmodule
- /////////////////////////////////////////////////
- module cnt_mux(CLK,CE_mux,Q_mux,CEO_mux);
- input CLK, CE_mux;
- output reg [27:0] Q_mux;
- output CEO_mux;
- always @(posedge CLK)
- if(CE_mux)
- if(Q_mux != 28'd49999999)
- Q_mux <= Q_mux + 1;
- else
- Q_mux <= 28'd0;
- assign CEO_mux = CE_mux & (Q_mux == 28'd49999999);
- endmodule
- ////////////////////////////////////////////////
- module dwojka(CLK, CE, Q_2);
- input CLK, CE;
- output reg Q_2;
- always @(posedge CLK)
- begin
- if(CE)
- Q_2 <= Q_2 +1;
- end
- endmodule
- ///////////////////////////////////////////////
- module SHF_REG(CLK,CE,Q);
- input CLK, CE;
- output [3:0] Q;
- reg [3:0] Q;
- always @(posedge CLK)
- if(CE)
- Q <= {Q[2:0],~&Q[2:0]};
- endmodule
- //////////////////////////////////////////////////////
- module mux(IN1, IN2, IN3, IN4, ADD, OUT_M);
- input [3:0] IN1, IN2, IN3, IN4;
- input [1:0] ADD;
- output [3:0] OUT_M;
- reg [3:0] OUT_M;
- always @(ADD or IN1 or IN2 or IN3 or IN4)
- case (ADD)
- 2'b00 : OUT_M = IN1;
- 2'b01 : OUT_M = IN2;
- 2'b10 : OUT_M = IN3;
- 2'b11 : OUT_M = IN4;
- //default : OUT_M = 4'b0000;
- endcase
- endmodule
- //////////////////////////////////////////////////////
- //module dekoder(IN_DEK, OUT_DEK);
- //input [3:0]IN_DEK;
- //output [1:0]OUT_DEK;
- //
- //reg [1:0]OUT_DEK;
- //
- //
- //always @(IN_DEK)
- //begin
- // case(IN_DEK)
- // 4'b1110 : OUT_DEK = 2'b00;
- // 4'b1101 : OUT_DEK = 2'b01;
- // 4'b1011 : OUT_DEK = 2'b10;
- // 4'b0111 : OUT_DEK = 2'b11;
- // default : OUT_DEK = 2'b00;
- // endcase
- //end
- //////////////////////////////////////////////////////
- ////////////////////////////////////////////////////
- module licznik_mux(CLK, CE, OUT_MUXC);
- input CLK, CE;
- output reg [1:0]OUT_MUXC;
- always @(posedge CLK)
- begin
- if(CE)
- OUT_MUXC <= OUT_MUXC + 1;
- end
- endmodule
- ////////////////////////////////////////////////////////
- module SEG7(BIN, SEG);
- input [3:0] BIN;
- output [6:0] SEG;
- reg [6:0] SEG;
- always @(BIN)
- case (BIN)
- 4'b0001 : SEG = 7'b1111001; // 1
- 4'b0010 : SEG = 7'b0100100; // 2
- 4'b0011 : SEG = 7'b0110000; // 3
- 4'b0100 : SEG = 7'b0011001; // 4
- 4'b0101 : SEG = 7'b0010010; // 5
- 4'b0110 : SEG = 7'b0000010; // 6
- 4'b0111 : SEG = 7'b1111000; // 7
- 4'b1000 : SEG = 7'b0000000; // 8
- 4'b1001 : SEG = 7'b0010000; // 9
- 4'b1010 : SEG = 7'b0001000; // A
- 4'b1011 : SEG = 7'b0000011; // b
- 4'b1100 : SEG = 7'b1000110; // C
- 4'b1101 : SEG = 7'b0100001; // d
- 4'b1110 : SEG = 7'b0000110; // E
- 4'b1111 : SEG = 7'b0001110; // F
- default : SEG = 7'b1000000; // 0
- endcase
- endmodule
- ////////////////////////////////////////////////////////////////
- module licznik_in(CLK, CE_in, Q_in);
- input CLK, CE_in;
- output [3:0]Q_in;
- reg [3:0]Q_in;
- always @(posedge CLK)
- begin
- if(CE_in)
- Q_in <= Q_in + 1;
- end
- endmodule
- ////////////////////////////////////////////////////////////////
- module final(SEG, CLK, CE, OUT, CEO,CEO_mux, CE_mux,OUT_MUXC,OUT_M, Q_in, OUT_2a, OUT_2b);
- input CLK, CE,CE_mux;
- //output [3:0] IN1, IN2, IN3, IN4;
- output [3:0]OUT;
- output [6:0]SEG;
- output CEO, CEO_mux;
- output OUT_2a, OUT_2b;
- output [1:0] OUT_MUXC;
- output [3:0] OUT_M, Q_in;
- //output [27:0] Q;
- //output [27:0] Q_mux; // dlaczego multipleksuje?
- reg [3:0] A=4'd2;
- reg [3:0] B=4'd3;
- reg [3:0] C=4'd4;
- wire [15:0] douta;
- //module cnt(CLK,CE,Q,CEO);
- cnt licznik(CLK,1'b1,Q,CEO);
- //module SHF_REG(CLK,CE,Q);
- SHF_REG rejestr(CLK, CEO, OUT);
- // module SEG7(BIN, SEG);
- SEG7 SEG1(OUT_M, SEG);
- //module mux(IN1, IN2, IN3, IN4, ADD, OUT_M)
- mux mux1(douta[15:12], douta[11:8],douta[7:4],douta[3:0],OUT_MUXC, OUT_M);
- //module cnt_mux(CLK,CE,Q_mux,CEO_mux);
- cnt_mux pres_mux(CLK,1'b1,Q_mux,CEO_mux);
- //module licznik_mux(CLK, CE, OUT_MUXC);
- licznik_mux licz_mux(CLK, CEO, OUT_MUXC);
- //module licznik_in(CLK, CE_in, Q_in)
- licznik_in li(CLK, CEO_mux, Q_in);
- //module dwojka(CLK, CE, Q_2);
- dwojka dwojk(CLK, CEO_mux, OUT_2a);
- dwojka dwojk1(CLK, CEO, OUT_2b);
- pam_progr your_instance_name (
- .clka(CLK), // input clka
- .addra(Q_in), // input [3 : 0] addra
- .douta(douta) // output [15 : 0] douta
- );
- endmodule
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