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tinymembench on ODROID N1 / A53

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Feb 16th, 2018
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  1. root@odroid:/home/odroid/tinymembench# taskset -c 1 ./tinymembench
  2. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  3.  
  4. ==========================================================================
  5. == Memory bandwidth tests ==
  6. == ==
  7. == Note 1: 1MB = 1000000 bytes ==
  8. == Note 2: Results for 'copy' tests show how many bytes can be ==
  9. == copied per second (adding together read and writen ==
  10. == bytes would have provided twice higher numbers) ==
  11. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  12. == to first fetch data into it, and only then write it to the ==
  13. == destination (source -> L1 cache, L1 cache -> destination) ==
  14. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  15. == brackets ==
  16. ==========================================================================
  17.  
  18. C copy backwards : 1410.1 MB/s (0.7%)
  19. C copy backwards (32 byte blocks) : 1422.9 MB/s (0.7%)
  20. C copy backwards (64 byte blocks) : 1402.5 MB/s (0.4%)
  21. C copy : 1459.3 MB/s (0.3%)
  22. C copy prefetched (32 bytes step) : 1053.6 MB/s (0.3%)
  23. C copy prefetched (64 bytes step) : 1199.7 MB/s (0.3%)
  24. C 2-pass copy : 1254.8 MB/s
  25. C 2-pass copy prefetched (32 bytes step) : 885.8 MB/s
  26. C 2-pass copy prefetched (64 bytes step) : 537.2 MB/s (0.6%)
  27. C fill : 4774.6 MB/s
  28. C fill (shuffle within 16 byte blocks) : 4770.6 MB/s (0.3%)
  29. C fill (shuffle within 32 byte blocks) : 4770.3 MB/s (0.3%)
  30. C fill (shuffle within 64 byte blocks) : 4771.3 MB/s (0.3%)
  31. ---
  32. standard memcpy : 1490.7 MB/s (0.3%)
  33. standard memset : 4777.8 MB/s (0.3%)
  34. ---
  35. NEON LDP/STP copy : 1522.1 MB/s (0.3%)
  36. NEON LDP/STP copy pldl2strm (32 bytes step) : 996.2 MB/s (0.8%)
  37. NEON LDP/STP copy pldl2strm (64 bytes step) : 1250.4 MB/s (0.3%)
  38. NEON LDP/STP copy pldl1keep (32 bytes step) : 1652.4 MB/s
  39. NEON LDP/STP copy pldl1keep (64 bytes step) : 1649.9 MB/s
  40. NEON LD1/ST1 copy : 1509.1 MB/s (0.5%)
  41. NEON STP fill : 4768.2 MB/s
  42. NEON STNP fill : 2932.2 MB/s (2.1%)
  43. ARM LDP/STP copy : 1526.3 MB/s
  44. ARM STP fill : 4772.7 MB/s (0.3%)
  45. ARM STNP fill : 2945.6 MB/s (2.0%)
  46.  
  47. ==========================================================================
  48. == Framebuffer read tests. ==
  49. == ==
  50. == Many ARM devices use a part of the system memory as the framebuffer, ==
  51. == typically mapped as uncached but with write-combining enabled. ==
  52. == Writes to such framebuffers are quite fast, but reads are much ==
  53. == slower and very sensitive to the alignment and the selection of ==
  54. == CPU instructions which are used for accessing memory. ==
  55. == ==
  56. == Many x86 systems allocate the framebuffer in the GPU memory, ==
  57. == accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
  58. == PCI-E is asymmetric and handles reads a lot worse than writes. ==
  59. == ==
  60. == If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
  61. == or preferably >300 MB/s), then using the shadow framebuffer layer ==
  62. == is not necessary in Xorg DDX drivers, resulting in a nice overall ==
  63. == performance improvement. For example, the xf86-video-fbturbo DDX ==
  64. == uses this trick. ==
  65. ==========================================================================
  66.  
  67. NEON LDP/STP copy (from framebuffer) : 200.7 MB/s
  68. NEON LDP/STP 2-pass copy (from framebuffer) : 185.0 MB/s (0.2%)
  69. NEON LD1/ST1 copy (from framebuffer) : 49.4 MB/s (0.2%)
  70. NEON LD1/ST1 2-pass copy (from framebuffer) : 48.1 MB/s (0.1%)
  71. ARM LDP/STP copy (from framebuffer) : 98.6 MB/s (0.1%)
  72. ARM LDP/STP 2-pass copy (from framebuffer) : 94.6 MB/s (0.2%)
  73.  
  74. ==========================================================================
  75. == Memory latency test ==
  76. == ==
  77. == Average time is measured for random memory accesses in the buffers ==
  78. == of different sizes. The larger is the buffer, the more significant ==
  79. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  80. == accesses. For extremely large buffer sizes we are expecting to see ==
  81. == page table walk with several requests to SDRAM for almost every ==
  82. == memory access (though 64MiB is not nearly large enough to experience ==
  83. == this effect to its fullest). ==
  84. == ==
  85. == Note 1: All the numbers are representing extra time, which needs to ==
  86. == be added to L1 cache latency. The cycle timings for L1 cache ==
  87. == latency can be usually found in the processor documentation. ==
  88. == Note 2: Dual random read means that we are simultaneously performing ==
  89. == two independent memory accesses at a time. In the case if ==
  90. == the memory subsystem can't handle multiple outstanding ==
  91. == requests, dual random read has the same timings as two ==
  92. == single reads performed one after another. ==
  93. ==========================================================================
  94.  
  95. block size : single random read / dual random read
  96. 1024 : 0.0 ns / 0.0 ns
  97. 2048 : 0.0 ns / 0.0 ns
  98. 4096 : 0.0 ns / 0.0 ns
  99. 8192 : 0.0 ns / 0.0 ns
  100. 16384 : 0.0 ns / 0.0 ns
  101. 32768 : 0.1 ns / 0.1 ns
  102. 65536 : 4.6 ns / 7.7 ns
  103. 131072 : 7.0 ns / 10.5 ns
  104. 262144 : 8.3 ns / 11.7 ns
  105. 524288 : 15.6 ns / 22.2 ns
  106. 1048576 : 102.9 ns / 155.0 ns
  107. 2097152 : 146.1 ns / 190.4 ns
  108. 4194304 : 170.6 ns / 207.5 ns
  109. 8388608 : 183.2 ns / 215.9 ns
  110. 16777216 : 191.6 ns / 221.7 ns
  111. 33554432 : 196.1 ns / 225.7 ns
  112. 67108864 : 198.9 ns / 230.3 ns
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