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-- Company:
-- Engineer:
--
-- Create Date: 11/19/2019 12:33:53 PM
-- Design Name:
-- Module Name: last - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity last is
  Port (x,rst,clk:in std_logic ;
        y:out std_logic);
end last;

architecture Behavioral of last is
type fast is (S0,S1,S2,S3,S4,S5,S6);
signal pr_state,nt_state : fast;
begin
    process (rst,clk)
        begin
        if(rst='1') then pr_state<=S0;
        elsif(rising_edge(clk))then
            pr_state<=nt_state;
        end if;
    end process;
    process (pr_state,x)
        begin
        case pr_state is
            when S0=> if(x='0')then
                        nt_state<=S1;
                        y<='1';
                      else
                        nt_state<=S2;
                        y<='0';
                      end if;
            when S1=> if(x='0')then
                        nt_state<=S3;
                        y<='1';
                      else
                        nt_state<=S4;
                        y<='0';
                      end if;
            when S2=> if(x='0')then
                        nt_state<=S4;
                        y<='0';
                      else
                        nt_state<=S4;
                        y<='1';
                      end if;
           when S3=>if(x='0')then
                      nt_state<=S5;
                      y<='0';
                    else
                      nt_state<=S5;
                      y<='1';
                    end if;
           when S4=>if(x='0')then
                      nt_state<=S5;
                      y<='1';
                    else
                      nt_state<=S6;
                      y<='0';
                    end if;
           when S5=>if(x='0')then
                      nt_state<=S0;
                      y<='0';
                    else
                      nt_state<=S0;
                      y<='1';
                    end if;
           when S6=>if(x='0')then
                       nt_state<=S0;
                       y<='1';
                    end if;
          end case;
    end process;
end Behavioral;