Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs

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Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs

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Reading design: fsm_tutor_3a.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fsm_tutor_3a.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fsm_tutor_3a"
Output Format                      : NGC
Target Device                      : xc7a100t-3-csg324

---- Source Options
Top Module Name                    : fsm_tutor_3a
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "/home/ise/PUR_LAB3/fsm_tutor_3a.vhd" into library work
Parsing entity <fsm_tutor_3a>.
Parsing architecture <behav> of entity <fsm_tutor_3a>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <fsm_tutor_3a> (architecture <behav>) from library <work>.
WARNING:HDLCompiler:92 - "/home/ise/PUR_LAB3/fsm_tutor_3a.vhd" Line 42: end_of_range should be on the sensitivity list of the process

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fsm_tutor_3a>.
    Related source file is "/home/ise/PUR_LAB3/fsm_tutor_3a.vhd".
    Found 3-bit register for signal <p_state>.
    Found 3-bit register for signal <addr_mux_reg>.
    Found 1-bit register for signal <end_of_range>.
    Found finite state machine <FSM_0> for signal <p_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | setup                                          |
    | Power Up State     | setup                                          |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Finite State Machine(s).
Unit <fsm_tutor_3a> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 2
 1-bit register                                        : 1
 3-bit register                                        : 1
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 4
 Flip-Flops                                            : 4
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <FSM_0> on signal <p_state[1:3]> with gray encoding.
------------------------
 State      | Encoding
------------------------
 setup      | 000
 measure    | 011
 regwrite   | 111
 outofrange | 010
 resync     | 110
 start      | 001
------------------------

Optimizing unit <fsm_tutor_3a> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm_tutor_3a, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 7
 Flip-Flops                                            : 7

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : fsm_tutor_3a.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 11
#      LUT2                        : 2
#      LUT3                        : 2
#      LUT5                        : 6
#      LUT6                        : 1
# FlipFlops/Latches                : 7
#      FD                          : 4
#      FDC                         : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 5
#      OBUF                        : 7

Device utilization summary:
---------------------------

Selected Device : 7a100tcsg324-3


Slice Logic Utilization:
 Number of Slice Registers:               7  out of  126800     0%
 Number of Slice LUTs:                   11  out of  63400     0%
    Number used as Logic:                11  out of  63400     0%

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     11
   Number with an unused Flip Flop:       4  out of     11    36%
   Number with an unused LUT:             0  out of     11     0%
   Number of fully used LUT-FF pairs:     7  out of     11    63%
   Number of unique control sets:         2

IO Utilization:
 Number of IOs:                          13
 Number of bonded IOBs:                  13  out of    210     6%

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 7     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 1.163ns (Maximum Frequency: 859.623MHz)
   Minimum input arrival time before clock: 0.803ns
   Maximum output required time after clock: 1.295ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.163ns (frequency: 859.623MHz)
  Total number of paths / destination ports: 30 / 7
-------------------------------------------------------------------------
Delay:               1.163ns (Levels of Logic = 1)
  Source:            addr_mux_reg_2 (FF)
  Destination:       addr_mux_reg_2 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: addr_mux_reg_2 to addr_mux_reg_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.361   0.697  addr_mux_reg_2 (addr_mux_reg_2)
     LUT5:I0->O            1   0.097   0.000  addr_mux_reg_2_rstpot (addr_mux_reg_2_rstpot)
     FD:D                      0.008          addr_mux_reg_2
    ----------------------------------------
    Total                      1.163ns (0.466ns logic, 0.697ns route)
                                       (40.1% logic, 59.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 9 / 6
-------------------------------------------------------------------------
Offset:              0.803ns (Levels of Logic = 2)
  Source:            ovf (PAD)
  Destination:       p_state_FSM_FFd3 (FF)
  Destination Clock: clk rising

  Data Path: ovf to p_state_FSM_FFd3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.001   0.697  ovf_IBUF (ovf_IBUF)
     LUT6:I0->O            1   0.097   0.000  p_state_FSM_FFd3-In1 (p_state_FSM_FFd3-In)
     FDC:D                     0.008          p_state_FSM_FFd3
    ----------------------------------------
    Total                      0.803ns (0.106ns logic, 0.697ns route)
                                       (13.2% logic, 86.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 13 / 7
-------------------------------------------------------------------------
Offset:              1.295ns (Levels of Logic = 2)
  Source:            p_state_FSM_FFd3 (FF)
  Destination:       clr_en (PAD)
  Source Clock:      clk rising

  Data Path: p_state_FSM_FFd3 to clr_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             11   0.361   0.558  p_state_FSM_FFd3 (p_state_FSM_FFd3)
     LUT3:I0->O            1   0.097   0.279  p_state__n0042<1>1 (ovf_flag_OBUF)
     OBUF:I->O                 0.000          ovf_flag_OBUF (ovf_flag)
    ----------------------------------------
    Total                      1.295ns (0.458ns logic, 0.837ns route)
                                       (35.4% logic, 64.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    1.163|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.64 secs

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Total memory usage is 600492 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)