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  1. uint8_t RC663_ISO14443A_UID(uint8_t *uid)
  2. {
  3. uint8_t result=0;
  4. quiet = 1;
  5. // Disable power down and pause ten milisecond before scanning.
  6. ioport_ext_set_pin_level(TCA6416_H_F_PDOWN, false);
  7. atomTimerDelay(1);
  8.  
  9. phhalSR( 0x0F, 0x98); // (Status: 0x0000)
  10. phhalSR( 0x14, 0x92); // (Status: 0x0000)
  11. phhalSR( 0x19, 0x20); // (Status: 0x0000)
  12. phhalSR( 0x1A, 0x03); // (Status: 0x0000)
  13. phhalSR( 0x1B, 0xFF); // (Status: 0x0000)
  14. phhalSR( 0x1E, 0x00); // (Status: 0x0000)
  15. _DEBUG("//< Configure FIFO Size=255 and Water-level");
  16. phhalGR( 0x02); // data == A0 // (Status: 0x0000)
  17. _DEBUG("//< Befor setting SR2 with 90");
  18. _DEBUG("//Value = 0xA0");
  19. _DEBUG("//< Configure FIFO Size=255 and Water-level");
  20. phhalSR( 0x02, 0x90); // (Status: 0x0000)
  21. phhalGR( 0x02); // data == A0 // (Status: 0x0000)
  22. _DEBUG("//< After setting SR2 with 90");
  23. _DEBUG("//Value = 0xA0");
  24. phhalSR( 0x03, 0xFE); // (Status: 0x0000)
  25. phhalSR( 0x0C, 0x80); // (Status: 0x0000)
  26. phhalGR( 0x28); // data == 89 // (Status: 0x0000)
  27. phhalSR( 0x28, 0x80); // (Status: 0x0000)
  28. phhalSR( 0x29, 0x00); // (Status: 0x0000)
  29. phhalSR( 0x2A, 0x01); // (Status: 0x0000)
  30. phhalSR( 0x2B, 0x05); // (Status: 0x0000)
  31. phhalSR( 0x34, 0x00); // (Status: 0x0000)
  32. phhalSR( 0x38, 0x12); // (Status: 0x0000)
  33. _DEBUG("//< =============================================");
  34. _DEBUG("//< 2. LoadProtocol( bTxProtocol=0, bRxProtocol=0)");
  35. _DEBUG("//< =============================================");
  36. _DEBUG("//< Terminate any running command. Flush_FiFo");
  37. phhalSR( 0x00, 0x00); // (Status: 0x0000)
  38. phhalSR( 0x02, 0xB0); // (Status: 0x0000)
  39. phhalSR( 0x06, 0x7F); // (Status: 0x0000)
  40. phhalSR( 0x07, 0x7F); // (Status: 0x0000)
  41. _DEBUG("//< Write in Fifo: Tx and Rx protocol numbers(0,0)");
  42. phhalGR( 0x04); // data == 00 // (Status: 0x0000)
  43. phhalSR( 0x05, 0x00); // (Status: 0x0000)
  44. phhalSR( 0x05, 0x00); // (Status: 0x0000)
  45. phhalGR( 0x08); // data == 00 // (Status: 0x0000)
  46. phhalSR( 0x08, 0x10); // (Status: 0x0000)
  47. phhalGR( 0x09); // data == 00 // (Status: 0x0000)
  48. phhalSR( 0x09, 0x40); // (Status: 0x0000)
  49. // The complete RFID scan takes longer than the time needed for led animation rates.
  50. // Call the led animation step routine halfway through to smooth things out. (should be safe but introduces a new hardware usage state so beware)
  51. // Block moved around experimentally to find this spot as the right balance to achieve resonsive RFID and smooth led animation.
  52. ui_LED_thread_step();
  53. _DEBUG("//< Start RC663 command Load Protocol=0x0d");
  54. phhalSR( 0x00, 0x0D); // (Status: 0x0000)
  55. phhalGR( 0x07); // data == 60 // (Status: 0x0000)
  56. phhalSR( 0x08, 0x00); // (Status: 0x0000)
  57. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  58. _DEBUG("//< Flush Fifo. Read Error Reg");
  59. phhalSR( 0x02, 0xB0); // (Status: 0x0000)
  60. phhalGR( 0x0A); // data == 00 // (Status: 0x0000)
  61. _DEBUG("//< Configure CRC-16 calculation, preset value(0x6363) for Tx&Rx");
  62. phhalSR( 0x2C, 0x18); // (Status: 0x0000)
  63. phhalSR( 0x2D, 0x18); // (Status: 0x0000)
  64. phhalSR( 0x2E, 0x08); // (Status: 0x0000)
  65. phhalSR( 0x2F, 0x20); // (Status: 0x0000)
  66. phhalSR( 0x30, 0x00); // (Status: 0x0000)
  67. phhalSR( 0x33, 0xCF); // (Status: 0x0000)
  68. phhalSR( 0x35, 0x04); // (Status: 0x0000)
  69. phhalSR( 0x37, 0x32); // (Status: 0x0000)
  70. phhalSR( 0x39, 0x00); // (Status: 0x0000)
  71. phhalSR( 0x36, 0x90); // (Status: 0x0000)
  72. phhalSR( 0x31, 0xC0); // (Status: 0x0000)
  73. phhalSR( 0x32, 0x0B); // (Status: 0x0000)
  74. phhalSR( 0x10, 0x08); // (Status: 0x0000)
  75. phhalSR( 0x11, 0xD8); // (Status: 0x0000)
  76. phhalSR( 0x15, 0x00); // (Status: 0x0000)
  77. phhalSR( 0x16, 0x00); // (Status: 0x0000)
  78. phhalSR( 0x28, 0x81); // (Status: 0x0000) // Tx2Inv, output pulled low
  79. _DEBUG("//< MIFARE Crypto1 state is further disabled.");
  80. phhalSR( 0x0B, 0x00); // (Status: 0x0000) // Disable crypto
  81. // The complete RFID scan takes longer than the time needed for perfect led animation.
  82. // Call the led animation step routine halfway through to smooth things out. (should be safe but introduces a new hardware usage state so beware)
  83. // Move this block around to find the right balance to achieve resonsive RFID and smooth led animation.
  84. ui_LED_thread_step();
  85.  
  86. // Experimental - Set the gain in the RxAna register
  87. phhalSR( 0x39, rfid_gain_setting); // (Status: 0x0000)
  88.  
  89.  
  90. _DEBUG("//< FieldOn");
  91. phhalSR( 0x28, 0x89); // (Status: 0x0000) // Tx2Inv, start transmitter,output pulled low
  92. _DEBUG("//< =============================================");
  93. _DEBUG("//< I14443p3a_Sw_RequestA");
  94. _DEBUG("//< =============================================");
  95. phhalSR( 0x31, 0xC0); // (Status: 0x0000) // TxWaitTime started at end of receive data, TxWait time is TxWait e 0.5 / DBFreq
  96. phhalSR( 0x32, 0x0B); // (Status: 0x0000) // minimum time between receive and send or between two send data streams
  97. _DEBUG("//< Set timeout for this command cmd. Init reload values for timers-0,1");
  98.  
  99. // Set the timer values to 0xffff. This changed the 0x63 to 0x61
  100. phhalSR( 0x10, 0xff); // (Status: 0x0000)
  101. phhalSR( 0x11, 0xff); // (Status: 0x0000)
  102. phhalSR( 0x15, 0xff); // (Status: 0x0000)
  103. phhalSR( 0x16, 0xff); // (Status: 0x0000)
  104.  
  105. phhalSR( 0x06, 0x08); // (Status: 0x0000) // enable TX IRQ
  106. phhalSR( 0x36, 0x90); // (Status: 0x0000) // Put 90 in rcvr wait register
  107. phhalSR( 0x2E, 0x0F); // (Status: 0x0000) // Put 0xf in TxDataNum reg
  108. _DEBUG("//< ---------------------");
  109. _DEBUG("//< Send the ReqA command");
  110. _DEBUG("//< ---------------------");
  111.  
  112.  
  113. _DEBUG("//< Terminate any running command. FlushFifo");
  114. phhalSR( 0x00, 0x00); // (Status: 0x0000)
  115. phhalSR( 0x02, 0xB0); // (Status: 0x0000) // Set fifo size to 255 and clear input fifo. Is actually setting bit 5 which is reserved ???
  116. phhalSR( 0x06, 0x7F); // (Status: 0x0000) // Enables all IRQ (does not include lowpower(
  117. phhalSR( 0x07, 0x7F); // (Status: 0x0000) // Clear all IRQs
  118. _DEBUG("//< Write ReqA=26 into FIFO");
  119. phhalSR( 0x05, 0x26); // (Status: 0x0000)
  120. _DEBUG("//< Start RC663 command Transcieve=0x07. Activate Rx after Tx finishes.");
  121. phhalSR( 0x00, 0x07); // (Status: 0x0000) // Issue a trasceive command. Transmit and then switch to recieve
  122. _DEBUG("//< Wait until the command is finished. Enable IRQ sources.");
  123. phhalSR( 0x08, 0x18); // (Status: 0x0000) // Enable Idle and TX IRQ
  124. phhalSR( 0x09, 0x42); // (Status: 0x0000) // Enable global IRQ and Timer1 IRQ
  125. phhalGR( 0x07); // data == 60 // (Status: 0x0000) // Reads back 0x61 or 0x63
  126. phhalSR( 0x08, 0x00); // (Status: 0x0000) // Clear SR1 and SR2
  127. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  128. // _DEBUG("//< Wait until reception");
  129. phhalSR( 0x08, 0x54); // (Status: 0x0000) // Enable LowAlert, Idle RX IRQ
  130. phhalSR( 0x09, 0x42); // (Status: 0x0000) // Enable Global IRQ and Timer1 IRQ
  131. phhalGR( 0x07); // data == 60 // (Status: 0x0000)
  132. phhalSR( 0x08, 0x00); // (Status: 0x0000)
  133. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  134.  
  135. _DEBUG("//< Read FIFO, expected: AtqA");
  136. phhalGR( 0x04); // data == 02 // (Status: 0x0000) // 0
  137. phhalGR( 0x05); // data == 44 // (Status: 0x0000) // 26
  138. phhalGR( 0x05); // data == 00 // (Status: 0x0000) // 26
  139. phhalGR( 0x0A); // data == 00 // (Status: 0x0000) // 0
  140. phhalSR( 0x2E, 0x08); // (Status: 0x0000)
  141.  
  142. static uint8_t this_reading[6];
  143.  
  144.  
  145. bool r=GET_UID_CL(1, this_reading, uid);
  146. if (r && this_reading[1] != 0x88)
  147. result = 4;
  148. else if(r && SELECT_CL(1, &this_reading[1]))
  149. {
  150. r=GET_UID_CL(2, this_reading, uid);
  151. if (r)
  152. result = 7;
  153. if(r && SELECT_CL(2, &this_reading[1]))
  154. {
  155. r = 0; //clear result flag
  156. result = 0;
  157. #if 0 //only if our uid array can support 10 bytes
  158. r=GET_UID_CL(3, this_reading, uid);
  159. if (r)
  160. result = 11;
  161. SELECT_CL(3, &this_reading[1]);
  162. #endif
  163. }
  164. }
  165.  
  166.  
  167. _DEBUG("//< =============================================");
  168. _DEBUG("//< Send HaltA cmd");
  169. _DEBUG("//< =============================================");
  170. phhalSR( 0x2E, 0x08); // (Status: 0x0000)
  171. _DEBUG("//< HaltA command needs CRC-16 appended to the data stream.");
  172. phhalSR( 0x2C, 0x19); // (Status: 0x0000)
  173. phhalSR( 0x2D, 0x19); // (Status: 0x0000)
  174. phhalSR( 0x0C, 0x00); // (Status: 0x0000)
  175. phhalSR( 0x08, 0x00); // (Status: 0x0000)
  176. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  177. phhalSR( 0x10, 0x3E); // (Status: 0x0000)
  178. phhalSR( 0x11, 0x58); // (Status: 0x0000)
  179. phhalSR( 0x15, 0x00); // (Status: 0x0000)
  180. phhalSR( 0x16, 0x00); // (Status: 0x0000)
  181. phhalSR( 0x00, 0x00); // (Status: 0x0000)
  182. phhalSR( 0x02, 0xB0); // (Status: 0x0000)
  183. phhalSR( 0x06, 0x7F); // (Status: 0x0000)
  184. phhalSR( 0x07, 0x7F); // (Status: 0x0000)
  185. _DEBUG("//< Write command data into FIFO");
  186. phhalSR( 0x05, 0x50); // (Status: 0x0000)
  187. phhalSR( 0x05, 0x00); // (Status: 0x0000)
  188. _DEBUG("//< Start the command (Transcieve)");
  189. phhalSR( 0x00, 0x07); // (Status: 0x0000)
  190. phhalSR( 0x08, 0x18); // (Status: 0x0000)
  191. phhalSR( 0x09, 0x42); // (Status: 0x0000)
  192. phhalGR( 0x07); // data == 63 // (Status: 0x0000)
  193. phhalSR( 0x08, 0x00); // (Status: 0x0000)
  194. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  195. _DEBUG("//< Wait until reception. Enable IRQ0 interrupt sources");
  196. phhalSR( 0x06, 0x40); // (Status: 0x0000)
  197. phhalSR( 0x08, 0x54); // (Status: 0x0000)
  198. phhalSR( 0x09, 0x42); // (Status: 0x0000)
  199. phhalGR( 0x07); // data == 63 // (Status: 0x0000)
  200. phhalSR( 0x08, 0x00); // (Status: 0x0000)
  201. phhalSR( 0x09, 0x00); // (Status: 0x0000)
  202. phhalSR( 0x00, 0x00); // (Status: 0x0000)
  203. phhalSR( 0x02, 0xB0); // (Status: 0x0000)
  204. phhalSR( 0x0E, 0x03); // (Status: 0x0000)
  205. phhalSR( 0x2E, 0x08); // (Status: 0x0000)
  206. _DEBUG("//< End of the script.");
  207. _DEBUG("//< .............................................");
  208.  
  209. // Shut the power back down
  210. ioport_ext_set_pin_level(TCA6416_H_F_PDOWN, true);
  211.  
  212. return result;
  213.  
  214. }
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